CS4525 datasheet(51/91 Pages) CIRRUS

51 / 91 page

DS726A1

CS4525

6.2.5

Digital Signal Flow

In hardware mode, the CS4525 operates as a 2-channel full-bridge PWM amplifier with analog or digital

inputs. To protect against over-temperature conditions, thermal foldback is included for the internal power

stages.

The digital signal flow is shown in Figure 14 below.

6.2.5.1

High-Pass Filter

The CS4525 includes a high-pass filter at the beginning of the digital signal processing chain to remove

any DC content from the input signal prior to the remaining internal digital signal processing blocks. The

high-pass filter operates by continuously subtracting a measure of the DC offset from the input signal; it

is always enabled.

6.2.5.2

Mute Control

The CS4525 includes a dedicated MUTE input pin. When low, the PWM outputs will output silence as an

exact non-modulated 50% duty cycle signal. When high, the selected input source will be presented at

the amplifier outputs.

It should be noted that the auto-mute, soft-ramp, and zero-crossing detection features available in soft-

ware mode are disabled in hardware mode.

6.2.5.3

Warning and Error Reporting

The CS4525 is capable of reporting various error and warning conditions on its TWR, ERROC, and ER-

RUVTE pins.

•The TWR pin indicates the presence of a thermal warning condition. When active concurrently with the

ERRUVTE pin, indicates a thermal error condition.

•The ERROC pin indicates the presence of an over-current condition on one or both of the output chan-

nels.

•

The ERRUVTE pin indicates the presence of a VP undervoltage or thermal error condition.

The trip point for each warning and error condition is defined in the PWM Power Output Characteristics

table on page 20. Each pin implements an active-low open-drain driver and requires an external pull-up

for proper operation.

Left

Full-Bridge

Amplifier

Output

Sample

Rate

Converter

PWM

Modulator

Sample

Rate

Converter

PWM

Modulator

Thermal Foldback

Temp & Current

Sense

ADC/SP

Stereo

Analog In

Serial Audio

Clocks & Data

I²S/LJ

Serial Audio

Input Port

Multi-Bit

∆Σ ADC

EN_TFB

Right

Full-Bridge

Amplifier

Output

Gate

Drive

Power

Stage

Gate

Drive

Power

Stage

Gate

Drive

Power

Stage

Gate

Drive

Power

Stage

TWR

ERROC

ERRUVTE

MUTE

Figure 23. Hardware Mode Digital Signal Flow

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