CS4525 datasheet(60/91 Pages) CIRRUS

60 / 91 page

DS726A1

CS4525

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each

byte is separated by an acknowledge bit.

7. PCB LAYOUT CONSIDERATIONS

7.1

Power Supply, Grounding

As with any high-resolution converter, the CS4525 requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling

capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS4525 as pos-

sible. The lowest value ceramic capacitor should be closest to the pin and should be mounted on the same

side of the board as the CS4525 to minimize inductance effects. All signals, especially clocks, should be

kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+

and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path

from FILT+ and AGND. The CRD4525 reference design demonstrates the optimum layout and power sup-

ply arrangements.

7.1.1

Integrated VD Regulator

The CS4525 includes two internal linear regulators, one from the VD supply voltage to provide a fixed 2.5

-V supply to its internal digital blocks, and another from the VD supply voltage to provide a fixed 2.5 - V

supply to its internal analog blocks. The LVD pin must be set to indicate the voltage present on the VD

pin as shown in Table 18 below.

The output of the digital regulator is presented on the VD_REG pin and may be used to provide an exter-

nal device with up to 3mA of current at its nominal output voltage of 2.5 - V. The output of the analog

regulator is presented on the VA_REG pin and must only be connected to the bypass capacitors as shown

in the typical connection diagrams.

If a nominal supply voltage of 2.5 V is used as the VD supply (see the Specified Operating Conditions

table on page 18), the VD, VD_REG, and VA_REG pins must all be connected to the VD supply source.

In this configuration, the internal regulators are bypassed and the external supply source is used to direct-

ly drive the internal digital and analog sections.

7.2

QFN Thermal Pad

The CS4525 is available in a compact QFN package. The underside of the QFN package reveals a large

metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with

an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of

thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB

layers. The CRD4525 reference design demonstrates the optimum thermal pad and via configuration.

LVD

Indicated VD Supply Level

Low

2.5 V or 3.3 V Nominal

High

5 V Nominal

Table 18. Input Source Selection

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