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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FS6407 датащи(PDF) 64 Page - NXP Semiconductors |
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FS6407 датащи(HTML) 64 Page - NXP Semiconductors |
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64 / 111 page  64 NXP Semiconductors FS6407/FS6408 7.2.1 Register address table Table 14 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for main logic. Table 15 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for fail-safe logic Table 14. Register mapping of main logic Register Address Write description Table ref. FS/M A4 A3 A2 A1 A0 Hex NOT USED 0 0000 0 #0(00h) N/A N/A INIT Vreg 1 0 0000 1 #1(01h) Write during INIT phase then read only Table 17 INIT Vreg2 0 0001 0 #2(02h) Write during INIT phase then read only Table 19 INIT CAN 0 0001 1 #3(03h) Write during INIT phase then read only Table 21 INIT IO_WU1 0 0010 0 #4(04h) Write during INIT phase then read only Table 23 INIT IO_WU2 0 0010 1 #5(05h) Write during INIT phase then read only Table 25 INIT INT 0 0011 0 #6(06h) Write during INIT phase then read only Table 27 NOT USED 0 0011 1 #7(07h) N/A N/A HW Config 0 0100 0 #8(08h) Read only Table 29 WU Source 0 0100 1 #9(09h) Read only Table 31 NOT USED 0 0101 0 #10(0Ah) N/A N/A IO_input 0 0101 1 #11(0Bh) Read only Table 33 Status Vreg#1 0 0110 0 #12(0Ch) Read only Table 35 Status Vreg#2 0 0110 1 #13(0Dh) Read only Table 37 Diag Vreg#1 0 0111 0 #14(0Eh) Read only Table 39 Diag Vreg#2 0 0111 1 #15(0Fh) Read only Table 41 Diag Vreg#3 0 1000 0 #16(10h) Read only Table 43 Diag CAN1 0 1000 1 #17(11h) Read only Table 45 Diag CAN 0 1001 0 #18(12h) Read only Table 47 Diag SPI 0 1001 1 #19(13h) Read only Table 49 NOT USED 0 1010 0 #20(14h) N/A N/A MODE 0 1010 1 #21(15h) Write during Normal and Read Table 51 Vreg Mode 0 1011 0 #22(16h) Write during Normal and Read Table 53 IO_OUT/AMUX 0 1011 1 #23(17h) Write during Normal and Read Table 55 CAN Mode 0 1100 0 #24(18h) Write during Normal and Read Table 57 CAN Mode 2 0 1100 1 #25(19h) Write during Normal and Read Table 59 Table 15. Register mapping of fail-safe logic Register Address Write description Table ref. FS/M A4 A3 A2 A1 A0 Hex INIT Supervisor#1 1 00001 #33(21h) Write during INIT phase then Read only Table 61 INIT Supervisor#2 1 00010 #34(22h) Write during INIT phase then Read only Table 63 INIT Supervisor#3 1 00011 #35(23h) Write during INIT phase then Read only Table 65 INIT FSSM#1 1 00100 #36(24h) Write during INIT phase then Read only Table 67 |
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