FS6407 datasheet(29/111 Pages) NXP

29 / 111 page

NXP Semiconductors

FS6407/FS6408

6.1.7

Low-power mode off

The Main State Machine has 3 LPOFF modes with different conditions to enter and exit each LPOFF mode as described here after. After

wake up from LPOFF, all the regulators are enabled by default. In LPOFF, all the regulators are switched OFF. The register configuration,

the VPRE behavior and the ISO pulse requirement are valid for the 3 LPOFF modes.

6.1.7.1

LPOFF - sleep

Entering in Low Power mode LPOFF - SLEEP is only available if the product is in Normal mode by sending a secured SPI command. In

this mode, all the regulators are turned OFF and the MCU connected to the VCORE regulator is unsupplied.

Before entering in LPOFF Power mode OFF-sleep, the Reset Error Counter must go back to value “0” (“N” consecutive good watchdog

refreshes decrease the reset error counter to 0). “N” = RSTb_err_2:0 x (WD_refresh_2:0 + 1). Once the FS6407/FS6408 is in LPOFF -

SLEEP, the device monitors external events to wake-up and leave the Low Power mode. The wake-up events can occur and depending

of the device configuration from:

•CAN

• I/O inputs

When a wake-up event is detected, the device starts the main state machine again by detecting the VPRE configuration (BUCK or BUCK-

BOOST), the wake-up source is reported to the dedicated SPI register, and the Fail-safe state machine is also restarted.

6.1.7.2

LPOFF - VPRE_UV

LPOFF- VPRE_UV is entered when the device is in the INIT or Normal mode, and if the VPRE voltage level is passing the VPRE_UV_L_4P3

threshold (typ 4.3 V). After 1.0 ms the device attempts to recover by switching ON the VPRE again.

6.1.7.3

LPOFF - deep FS

LPOFF - DEEP FS is entered when the device is in Deep Fail-safe and if the Key is OFF (IO_0 is low). To exit this mode, a transition to

high level on IO_0 is required. IO_0 is usually connected to key ON key OFF signal.

6.1.7.4

In LPOFF, the register settings of the main state machine are kept because the internal 2.5 V main digital regulator is available for wake-

up operation. However, the register settings of the fail-safe state machine are erased, because the 2.5 V fail safe digital regulator is not

available in LPOFF. As a consequence, after a wake-up event, the configuration of the fail-safe registers must be done again during

initialization phase (256 ms open window).

6.1.7.5

VPRE behavior in LPOFF

When device is in LPOFF Sleep mode, and if the VSUP < VSUP_UV_7, VPRE is switched on to maintain internal biasing and wake-up

capabilities on IOs or CAN.

•If VPRE is configured as a non-inverting buck-boost converter, VPRE is switched ON in SMPS mode with boost functionality.

•If VPRE is configured as a standard buck converter, VPRE is switched ON in Linear mode following VSUP.

6.2

Mode and state description of fail-safe state machine

6.2.1

LBIST

Included in the fail-safe machine, the Logic Built-in Self Test (LBIST) verifies the correct functionality of the FSSM at start-up. The fail-safe

state machine is fully checked and if an issue is reported, the RSTB stays low and after 8 s, the device enters in DEEP Fail-safe. LBIST

is run at start-up and after each wake-up event when the device is in LPOFF mode.

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