FS6407 datasheet(61/111 Pages) NXP

61 / 111 page

NXP Semiconductors

FS6407/FS6408

Serial peripheral interface

7.1

High level overview

7.1.1

SPI

The device is using a 16-bit SPI, with the following arrangement:

MOSI, Master Out Slave In bits:

• Bit 15 read/write

• Bit 14 Main or fail-safe register target

• bit 13 to 9 (A4 to A0) to select the register address. Bit 8 is a parity bit in write mode, Next bit (=0) in read mode.

• bit7 to 0 (D7 to D0): control bits

MISO, Master IN Slave Out bits:

• bits 15 to 8 (S15 to S8) are device status bits

• bits 7 to 0(Do7 to Do0) are either extended device status bits, device internal control register content or device flags.

Figure 47 is an overview of the SPI implementation.

7.1.2

Parity bit 8 calculation

The parity is used for write to register command (bit 15,14 = 01). It is calculated based on the number of logic ones contained in bits

15-9, 7-0 sequence (this is the whole 16-bits of the write command except bit 8).

Bit 8 must be set to 0 if the number of 1 is odd.

Bit 8 must be set to 1 if the number of 1 is even.

7.1.3

Device status on MISO

When a write operation is performed to store data or control bit into the device, MISO pin reports a 16-bit fixed device status composed

of two bytes: Device Fixed Status (bits 15 to 8) + extended Device Status (bits 7 to 0). In a read operation, MISO reports the fixed device

status (bits 15 to 8), and the next eight bits are content of the selected register. A standard serial peripheral interface (SPI) is integrated

to allow bi-directional communication between the FS6407/FS6408 and the MCU. The SPI is used for configuration and diagnostic

purposes.

Figure 47. SPI overview

Bit 15

Bit 13

Bit 11

Bit 12

Bit 10

Bit 14

Bit 9 Bit 8

R/W

M/FS

Bit 7

Bit 5

Bit 3

Bit 4

Bit 2

Bit 6

Bit 1 Bit 0

Parity

data

MOSI

S15

S13

S11

S14

Do7

Do5

Do3

Do4

Do2

Do6

Do1

Do0

S12

S10

MISO

Device Status

Extended Device Status, Register Control bits or Device Flags

CSb

SCLK

MOSI

MISO Tri state

Tri state

SPI wave form, and signals polarity

S15

S14

Do0

SCLK signal is low outside of CSB active

CSb active low. Must be raised at end of 16 clocks,

MOSI and MISO data changed at SCLK rising edge

and sampled at falling edge. Msb first.

MISO tri state outside of CSB active

Don’t care

for write commands, MOSI bits [15] = [1].

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