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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FS6407 датащи(PDF) 32 Page - NXP Semiconductors |
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FS6407 датащи(HTML) 32 Page - NXP Semiconductors |
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32 / 111 page  32 NXP Semiconductors FS6407/FS6408 6.4 Functional state diagram Figure 10. Simplified state diagram CAN/IOs event LPOFF - VPRE_UV LPOFF - DEEP FS From Anywhere VSUP < VSUP_UV_L Buck or Buck Boost configuration detection PowerDown VSUP > VSUP_UV_5 120µs elapsed VPRE ON VPRE>VPRE_UV SELECT pin config. detection VPRE<VPRE_UV 1ms elapsed Vcore/Vaux/ Vcca ON INIT MAIN INIT done (init int reg. writing) NORMAL MODE LPOFF - SLEEP Wake up SPI command From Anywhere PowerDown LBIST LBIST Done & VPRE>VPRE_UV SELECT pin config. detection 1ms elapsed & VCORE > VCORE_UV & VCCA > VCCA_UV & VAUX > VAUX_UV ABIST VPRE<VPRE_UV Release RSTb INIT FS NORMAL WD is RUNNING RST Delay ABIST Pass No external RST & No activate RST WD OK External RST Activate RST or WD Not OK Activate RST Activate RST External RST External RST No activate RST & RST delay expired Rise IO_0 - RSTb is asserted low - RSTb is asserted low - RSTb is asserted low - RSTb is released - Unlock SPI init registers - Start 256ms open window - RSTb is released - Start WD close/open window - Unlock SPI init registers - SPI config - SPI init registers locked MAIN STATE MACHINE FAIL SAFE STATE MACHINE Activate RST : any UV, any OV, WD, IO_23 error, deep fail safe, reset by spi, IO_1 FB_core delta, FS0b short to VDD, SPI DED - VCAN/VCORE OFF - VAUX/VCCA OFF - OSC Main ON - FailSafe ON - VCAN/VCORE/VAUX/VCCA OFF - Fail Safe OFF - RSTb delay running - RSTb is asserted low POR Fail Safe No POR Fail Safe VPRE_UV_L4P3 VPRE_UV_L4P3 Wait Fail SAFE POR Fail Safe & Fail Safe Reg. ON & VSUP > VSUP_UV_5 VSUP <VSUP_UV_5 VSUP < VSUP_UV_5 POR Fail Safe & Fail Safe Reg. ON 1ms Wait Deep Fail Safe RST delay=8s or RST error counter = 6 No IO_0 Vpre OFF Vpre ON |
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