FS6407 datasheet(22/111 Pages) NXP

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NXP Semiconductors

FS6407/FS6408

Functional pin description

5.1

Introduction

The FS6407/FS6408 is the third generation of the System Basis Chip, combining:

• High efficiency switching voltage regulator for MCU, and linear voltage regulators for integrated CAN interface, external ICs such as

sensors, and accurate reference voltage for A to D converters.

• Built-in enhanced high-speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostic, protection, and Fail-safe

operation mode.

• Low-power mode, with ultra low-current consumption.

• Various wake-up capabilities.

• Enhanced safety features with multiple fail-safe outputs and scheme to support SIL applications.

5.2

Power supplies (VSUP1, VSUP2, VSUP3)

VSUP1 and VSUP2 are the inputs pins for internal supply dedicated to SMPS regulators. VSUP3 is the input pin for internal voltage

reference. VSUP1, 2, and 3 are robust against ISO7637 pulses. VSUP1,2, and 3 must be connected to the same supply (Figure 49).

5.3

VSENSE input (VSENSE)

This pin must be connected to the battery line (before the reverse battery protection diode), via a serial resistor. It incorporates a threshold

detector to sense the battery voltage, and provide a battery early warning. It also includes a resistor divider to measure the VSENSE

voltage via the MUX-OUT pin. VSENSE pin is robust against ISO7637 pulses.

5.4

Pre-regulator (VPRE)

A highly flexible SMPS pre-regulator is implemented in the FS6407/FS6408. It can be configured as a “non-inverting buck-boost converter”

(Figure 24) or “standard buck converter” (Figure 23), depending on the external configuration (connection of pin GATE_LS). The

configuration is detected automatically during start-up sequence.

The SMPS pre-regulator is working in current mode control and the compensation network is fully integrated in the device. The high-side

switching MOSFET is also integrated to make the current control easier. The pre-regulator delivers a typical output voltage of 6.5 V, which

is used internally. Current limitation, overcurrent, overvoltage, and undervoltage detectors are provided. VPRE is enabled by default.

5.5

VCORE output (from 1.2 V to 3.3 V range)

The VCORE block is an SMPS regulator. The voltage regulator is a step down DC-DC converter operating in voltage control mode. The

output voltage is configurable from 1.2 V to 3.3 V range thanks to an external resistor divider connected between VCORE and the

feedback pin (FB_CORE) (as example in Figure 1, Figure 2, and Figure 49).

The stability of the converter is done externally, by using the COMP_CORE pin. Current limitation, overvoltage, and undervoltage

detectors are provided. VCORE can be turned ON or OFF via a SPI command, however it is not recommended to turn OFF VCORE by

SPI when VCORE is configured safety critical (both overvoltage and undervoltage have an impact on RSTB and FS0B). VCORE

overvoltage information disables VCORE. Diagnostics are reported in the dedicated register and generate an Interrupt. VCORE is enabled

by default.

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