AT25QL641 datasheet(25/80 Pages) RENESAS

25 / 80 page

DS-AT25QL641-130 Rev. G

Page 25

Sep 14, 2022

AT25QL641 Datasheet

8.6

Write Status Register (01h)

The Write Status Register command is u s e d to write only t h e non-volatile Status Register-1 bit SRP0, and

Status Register-2 bits QE and SRP1. All other Status Register bit locations are read-only and are not affected by

the Write Status Register command.

A Write Enable (06h) command must previously have been issued prior to setting Write Status Register

Command (Status Register bit WEL must equal 1). Once the WEL bit is set, the command is entered by driving CS

low, sending the command code, and then writing the status register data byte as illustrated in Figure 10 and

Figure 11.

The CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done, the

Write Status Register command is not executed. If CS is driven high after the eighth clock, the CMP, QE and

SRP1 (Status Register 2) bits are cleared to 0. After CS is driven high, the self- timed Write Status Register cycle

commences for a time duration of tW (see Table 26, AC Electrical Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register command may still be accessed to

check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when

the cycle is finished and ready to accept other commands again. When the BUSY bit is asserted, the Write

Enable Latch (WEL) bit in Status Register is cleared to 0.

Figure 10. Write Status Register Command (SPI Mode)

Figure 11. Write Status Register Command (QPI Mode)

SCK

Mode 3

Mode 0

Mode 3

Mode 0

MSB

Status Register-1 in

Command

01h

High-Impedance

MSB

Status Register-2 in

SCK

Command

01h

SR1

SR2

Mode 3

Mode 0

Mode 3

Mode 0

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