AT25QL641 datasheet(43/80 Pages) RENESAS

43 / 80 page

DS-AT25QL641-130 Rev. G

Page 43

Sep 14, 2022

AT25QL641 Datasheet

8.20 Chip Erase (C7h / 60h)

The Chip Erase command sets all bits in the memory to 1. Prior to the Chip Erase command, a Write Enable (06h)

command must be issued. The command is initiated by driving the CS pin low and shifting the command code

C7h or 60h. See Figure 35 below. The CS pin must go high after the eighth bit of the last byte has been latched

in, otherwise, the Chip Erase command is not executed. After CS is driven high, the self-timed Chip Erase

command commences for a duration of tCE (see Table 26, AC Electrical Characteristics).

While the chip erase operation is in progress, the Read Status Register (05h) command may still be accessed to

check the status of the BUSY bit. The BUSY bit is 1 during the chip erase operation and becomes a 0 when the

cycle is finished and the device is again ready to accept other commands. When the BUSY bit is asserted, the

Write Enable Latch (WEL) bit in the Status Register is cleared to 0.

Figure 35. Chip Erase Command for SPI Mode (left) and QPI Mode (right)

8.21 Erase / Program Suspend (75h)

The Erase/Program Suspend command allows the system to interrupt a Block Erase operation, or a Page

Program, Quad Data Input Page Program, Quad Page Program operation.

The Erase Suspend is valid only during the Block or Block erase operation. The Write Status Register-1 (01h),

Write Status Register-2 (31h) command and Erase commands (20h, 52h, D8h, C7h, 60h) are not allowed during

an Erase Suspend operation. During the Chip Erase operation, the Erase Suspend command is ignored.

Program Suspend is valid only during the Page Program, Quad Data Input Page Program or Quad Page Program

operation. The Write Status Register-1 (01h), Write Status Register-2 (31h) command, Program commands (02h

and 33h) and Erase Commands (20h, 52h, D8h, C7h, 60h) are not allowed during Program Suspend.

The Erase/Program Suspend command 75h is accepted by the device only if the SUS bit in the Status Register

equals to 0 and the BUSY bit equals to 1 while a Block Erase or a Page Program operation is on-going. If the

SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend command is ignored by the device. A maximum

time of tSUS (see Table 26, AC Electrical Characteristics) is required to suspend the erase or program operation.

After Erase/Program Suspend, the SUS bit in the Status Register is set (0 to 1) immediately and the BUSY bit in

the Status Register is cleared (1 to 0) within tSUS. For a previously resumed Erase/Program operation, it is also

required that the Suspend command 75h is not issued earlier than a minimum of time of tSUS following the

preceding Resume command 7Ah.

A read operation from an 8-Mbit area (referred to as a physical block) that includes a suspended area might

provide unreliable data. For the definition of the physical block and for the techniques to ensure high data integrity,

see application note AN-500.

246

Mode 3

Mode 0

Mode 3

Mode 0

High-Impedance

SCK

Command (C7h/60h)

Command

(C7h/60h)

Mode 3

Mode 0

Mode 3

Mode 0

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