AT25QL641 datasheet(14/80 Pages) RENESAS

14 / 80 page

DS-AT25QL641-130 Rev. G

Page 14

Sep 14, 2022

AT25QL641 Datasheet

Status Registers

The Read Status Register command can be used to provide status on the availability of the Flash memory array, if

the device is write enabled or disabled, the state of write protection, and the Quad SPI setting. The Write Status

access to the Status register is controlled, in some cases, by the WP pin.

7.1

Busy

BUSY is a read-only bit (S0) that is set to a 1 state when the device is executing a Page Program, Erase, Write

Status Register or Write Security Register command. During this time, the device ignores further command except

for the Read Status Register and Erase / Program Suspend command (see tW, tPP, tSE, tBE1, tBE2 and tCE in Table

26, AC Electrical Characteristics). When the Program, Erase, Write Status Register or Write Security Register

command has completed, hardware clears the BUSY bit (to a 0 state), indicating the device is ready for further

commands.

7.2

Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in status register (S1) that is set to a 1 after executing a Write Enable

command. The WEL status bit is cleared to a 0 when device is write disabled. A write disable state occurs upon

power-up or after any of the following commands: Write Disable, Page Program, Erase and Write Status Register.

7.3

Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits (S4, S3, and S2) that provide write

protection control and status. Block protect bits can be set using the Write Status Register Command (see tW in

Table 26, AC Electrical Characteristics). All, none or a portion of the memory array can be protected from Program

and Erase commands (see Table 5 and Table 6). The factory default setting for the Block Protection Bits is 0, none

of the array protected.

7.4

Top/Bottom Block Protect (TB)

The Top/Bottom bit (TB) is non-volatile bits (S5) that controls if the Block Protect Bits (BP2, BP1, BP0) protect

from the Top (TB = 0) or the Bottom (TB = 1) of the array, as shown in Table 5 and Table 6. The factory default

setting is TB = 0. The TB bit can be set with the Write Status Register Command depending on the state of the

SRP0, SRP1, and WEL bits.

Table 2. Status Register-1

SRP

SEC

BP2

BP1

BP0

WEL

BUSY

Status

Protect 0

(Non- Volatile)

Sector

Protect (Non-

Volatile)

Top/Bottom

Write Protect

(Non- Volatile)

Block Protect

(Non-

Volatile)

Block Protect

(Non-

Volatile)

Block Protect

(Non-

Volatile)

Write Enable

Latch

Erase or

Write in

Progress

Table 3. Status Register-2

S15

S14

S13

S12

S11

S10

SUS

CMP

(R)

SRP1

Suspend

Status

Complement

Protect

(Non-Volatile)

Reserved

Quad Enable

(Non-Volatile)

Protect 1

(Non-Volatile)

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