AT25QL641 datasheet(9/80 Pages) RENESAS

9 / 80 page

DS-AT25QL641-130 Rev. G

Page 9

Sep 14, 2022

AT25QL641 Datasheet

SO (I/O1)

SERIAL OUTPUT

The SO pin is used to shift data out from the device. Data on the SO pin is always

clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in

conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on every

falling edge of SCK.

To maintain consistency with the SPI nomenclature, the SO (I/O1) pin is referenced as

the SO pin unless specifically addressing the Dual-I/O modes in which case it is

referenced as I/O1. The SO pin is in a high-impedance state whenever the device is

deselected (CS is deasserted).

Input/Output

(I/O2)

WRITE PROTECT

The Write Protect (WP) pin can be used to protect the Status Register against data

modification. Used with the Status Register's Block Protect (SEC, TB, BP2, BP1 and

BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array

can be hardware protected. The WP pin is active low. When the QE bit of Status

available because this pin is used for IO2. The WP pin does not have an internal pull-

up; thus, it must be either driven or, if not used, pulled up with an external resistor to

VCC.

Input/Output

HOLD

(I/O3)

HOLD

The HOLD pin is used to temporarily pause serial communication without deselecting or

resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and

data on the SI pin are ignored, and the SO pin is placed in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a

Hold condition to start. A Hold condition pauses serial communication only and does not

have an effect on internally self-timed operations such as a program or erase cycle.

With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input

pin (I/O3) and with other pins, allows four bits (on I/O3-0) of data to be clocked in on

every rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin

becomes an output pin (I/O3) in conjunction with other pins to allow four bits of data on

(I/O33-0) to be clocked in on every falling edge of SCK. To maintain consistency with

SPI nomenclature, the HOLD (I/O3) pin is referenced as the HOLD pin unless

specifically addressing the Quad-I/O modes, in which case it is referenced as I/O3. The

HOLD pin does not have an internal pull-up; thus, it must be either driven or, if not used,

pulled up with an external resistor to VCC.

Input/Output

VCC

DEVICE POWER SUPPLY

VCC is the supply voltage. It is the single voltage used for all device functions including

read, program, and erase. The VCC pin is used to supply the source voltage to the

device. Operations at invalid VCC voltages may produce spurious results and should

not be attempted.

Power

GND

GROUND

VSS is the reference for the VCC supply voltage. The ground reference for the power

supply. GND should be connected to the system ground.

Power

Table 1. Pin Descriptions (Continued)

Symbol

Name and Function

Asserted

State

Type

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