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AT25QL641 датащи(PDF) 22 Page - Renesas Technology Corp

номер детали AT25QL641
подробное описание детали  SPI Serial Flash Memory with Dual I/O, Quad I/O, QPI Support
PDF  80 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25QL641 датащи(HTML) 22 Page - Renesas Technology Corp

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DS-AT25QL641-130 Rev. G
Page 22
Sep 14, 2022
© 2022 Renesas Electronics
AT25QL641 Datasheet
8.2
Write Enable (06h)
The Write Enable command is used for setting the Write Enable Latch (WEL) bit in the Status Register. The WEL
bit must be set prior to every Program, Erase and Write Status Register command. To execute the Write Enable
command, drive CS glow prior to driving command 06h onto the SI pin on the rising edge of SCK, and then
driving CS high.
Figure 5. Write Enable Command for SPI Mode (left) and QPI Mode (right)
Fast Read
Quad I/O[6]
up to 80
MHz
EBh
A23:A16
A15:A8
A7:A0
(M7:M0
)
Dummy
(D7:D0)
up to 104
MHz
A23:A16
A15:A8
A7:A0
(M7:M0)
Dummy
Dummy
(D7:D0)
up to 133
MHz
A23:A16
A15:A8
A7:A0
(M7:M0
)
Dummy
Dummy
Dummy (D7:D0)
Reset Enable
66h
Reset
99h
Disable QPI
FFh
Burst Read
with Wrap
up to 80
MHz
0Ch
A23:A16
A15:A8
A7:A0
Dummy
Dummy
(D7:D0)
up to 104
MHz
A23:A16
A15:A8
A7:A0
Dummy
Dummy
Dummy
(D7:D0)
up to 133
MHz
A23:A16
A15:A8
A7:A0
Dummy
Dummy
Dummy
Dummy (D7:D0)
Quad Page Program
33h
A23:A16
A15:A8
A7:A0
(D7:D0)
1.
Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis () indicate data being read from the device on the I/O pin.
2.
SR = Status Register. The Status Register contents and Device ID repeat continuously until CS terminates the command.
3.
At least one byte of data input is required for Page Program, Quad Page Program and Program Security Register, up to 256 bytes of data input. If more
than 256 bytes of data are sent to the device, the address wraps to the beginning of the page and overwrite previously sent data.
4.
See Table 7 for Device ID information.
5.
SC = Security Register.
6.
The M7-M0 bits are counted as dummy clocks.
Table 11. Command Set Table 4 (QPI Commands) (Continued)
Command Byte[1]
0
1
2
345
6
7
8
Clock Number
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
03
5
246
7
1
Mode 3
Mode 0
Mode 3
Mode 0
High-Impedance
SO
SI
IO
IO
IO
IO
SCK
SCK
CS
Command
0
1
Mode 3
Mode 0
Mode 3
Mode 0
CS
(06h)
Command
06h



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