MEC1632 datasheet(98/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 98

 2012-2018 Microchip Technology Inc.

7.4

Clock Generator

7.4.1

OVERVIEW

The MEC1632 Clock Generator includes clock sources as illustrated in Figure 7-1, "Clock Generator Block Diagram":

the 20 MHz Oscillator and 32K Clock Domain, as well as the PCI Clock (PCI_CLK in Table 7-4). The relationship of

these clock sources to the system power supplies is described in Section 7.4.2, "Power Supplies and Clocking," on

page 99; their relationship to the ACPI power states is described in Section 7.5.1, "Power Supplies and Clocks ACPI

Context," on page 121.

MCLK Sourced Clocking includes Programmable Clock Domains, a Fixed Clock Domain and a Host Clock

Domain. The output from the 32.768 KHz Silicon Oscillator, or 32.768 KHz Crystal Oscillator or a 32 KHz external input

clock defines a 32K Clock Domain.

The Clock Generator also includes the definition of a Generic Block Clocking Model that provides the foundation for a

Power Management Interface. This interface defines several EC Controlled Dynamic Power States that can influence

power consumption at the block level and within the Clock Generator.

The Clock Generator includes an EC accessible Registers Interface.

RESETI#

Input

External

RESET Pin Inter-

face

See Section 7.6.3, "RESET Pin Inter-

face," on page 126.

AVTRGD

Output

Internal

VBAT-Powered

Control Interface

Delayed ALLGD signal in FIGURE 7-18:

Reset Interface Block Diagram on

page 125.

TABLE 7-4:

Power, Clocks, and Resets Port List (CONTINUED)

Signal Name

Direction

Source

Destination

Description

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