MEC1632 datasheet(64/636 Pages) MICROCHIP

64 / 636 page

MEC1632

DS00001592B-page 64

 2012-2018 Microchip Technology Inc.

The Host can only access a subset of the AHB address space, and within that space all registers are treated as 8-bit

registers, although a register may be implemented as a 32-bit register and accessible to the EC as a 32-bit register. The

Host accesses registers in the FF_0000h through FF_FFFFh range through LPC I/O cycles. I/O cycles are mapped

according to rules described in Section 5.5, on page 65 and Section 5.6, on page 66.

5.4

Registers

The Host Interface has its own Logical Device Number and Base Address as indicated in Table 5-2. The Host LPC I/O

addresses for the Logical Device Configuration are selected via a Base Address Register. LPC access to configuration

registers is through the Host Access Configuration Port

The Logical Device Configuration also has a Global Configuration block which has a separate Logical Device Number

and Base Address Register as indicated in Table 5-2. The Base Address Register for the Global Configuration has only

one writable bit, the Valid Bit, since the only I/O accessible Register has a fixed address.

Table 5-3 is a register summary for the LPC Interface block and Table 5-15, “Chip-Level (Global) Control/Configuration

Registers,” on page 78 is a register summary for the Global Configuration block.

Table 5-3 is a register summary for the Host Access Port block. The LPC I/O address for each Run-Time Register is

described below as an offset from its Base Address Register. Each EC address is indicated as an SPB Offset from its

AHB base address. Each Configuration register access through the Host Access Port address via its LDN indicated in

Table 5-2 on page 64 and its Host Access Port index which is described as “Host Config Index” in the tables below.

TABLE 5-2:

Host Interface BASE ADDRESS TABLE

Host Interface

Blocks

LDN from

(

Table 4-2 on

page 59)

AHB Base Address

LPC Interface

FF_3000h

Global Configuration

3Fh

FF_FC00h

Note:

The Host LPC I/O addresses for this instance are selected via a Base Address Register (see Section 5.6.2,

on page 66). LPC access to configuration registers is through the Host Access Configuration Port (see

Section 5.5.1, on page 65).

TABLE 5-3:

Host Access Port REGISTER SUMMARY

Host I/O Access

EC Interface

Notes

Port Name

Host I/O Index

SPB Offset

Host

Type

SPB Offset

Byte

Lane

EC Type

CONFIG PORT

00h

INDEX PORT

00h

R/W

DATA PORT

01h

R/W

Note:

The EC does not have access to the Host Access Port; however, the EC can access registers with AHB

addresses.

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