MEC1632 datasheet(97/636 Pages) MICROCHIP

97 / 636 page

 2012-2018 Microchip Technology Inc.

DS00001592B-page 97

MEC1632

32KHZ_OUT

Output

Internal

External

Off-Chip 32.768KHz Oscillator Output

(see "32KHz OUTPUT," on page 135).

ALL BLOCK

“CLOCK

REQUIRED” STA-

TUS BITS

Input

External -

Sleep-able

Blocks

Internal - 20 MHz

Oscillator Control

see Section 7.8.5, "Clock Required Sta-

tus Registers," on page 140.

nSIO_RESET

Output

Internal

Internal/ External

EC-driven SIO Reset and External Sys-

tem Reset (nRESET_OUT pin). (see

"iRESET OUT," on page 133).

VCC_PWRGD

Input

External

Internal -Host

Clock Domain

VCC Power Good Input. See Section

7.4.11.4, "Host Clock Domain," on

page 120 and Section 7.7.2, "VCC

Power Good," on page 129. The EC

can determine the state of the VCC_P-

WRGD signal using VCC PWRGD bit in

the Block Sleep Enable Registers. See

also Section 7.7.3, "LPC RESET," on

page 129.

VCC_PWRG-

D_BUFF

Output

Internal

External - Pad

Buffers

Buffered VCC_PWRGD output used to

tri-state VCC-related Pads.

PCR_INT

Output

Internal

External ("EC

Interrupt Aggrega-

tor," on page 287)

see Section 7.10, "Interrupt Interface,"

on page 150.

FLASH_PGM

Input

External

Internal - Power-

Fail and Reset

Status Register

see "FLASH," on page 148.

LPC_RST#

Output

Internal

External (LPC

Interface)

see Section 7.7.3, "LPC RESET," on

page 129.

VTR

Power Well

External

–

Suspend Supply

VBAT

Power Well

External

–

Battery Supply

VSS

Power Well

External

–

Digital Ground

AGND

Power Well

External

–

Analog Ground for the 32.768 KHz Sili-

con Oscillator.

VTR_1.8

Power Well

Internal

–

Output of the internal 1.8 V regulator

(see Section 7.7, "1.8V Regulator," on

page 128).

VTR1.8_BAT

Power Well

Internal

–

Output of the internal Power Mux for

VBAT-backed logic (see Section 7.7.1,

"Power Mux," on page 129).

nSYS_RST

Output

Internal

Internal/ External

Synchronized VTR Power Good (Sec-

tion 7.6.6, "nSYS_RST," on page 128).

nEC_RST

Output

Internal

Internal/ External

Stretched nSYS_RST used for EC reset

and Registers Interface (see Section

7.6, "Reset Interface," on page 124).

VBAT_POR

Output

Internal

Internal/ External

VBAT Power On Reset (Section 7.6.5,

"VBAT_POR," on page 128)

VR_CAP

Power Well

Internal

–

Capacitor Connection for Internal

Voltage Regulator (4.7

F ±20%, ESR 2

Ohms, max.) (see also Section 7.7,

"1.8V Regulator," on page 128).

TABLE 7-4:

Power, Clocks, and Resets Port List (CONTINUED)

Signal Name

Direction

Source

Destination

Description

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