MEC1632 datasheet(71/636 Pages) MICROCHIP

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DS00001592B-page 71

MEC1632

5.6.6

MAPPING LPC MEMORY ADDRESSES

This section is the same as Mapping LPC I/O Addresses on page 67 except that the LPC memory cycle address is 32

bit instead of the I/O cycle 16 bit.

5.6.7

MEMORY BASE ADDRESS REGISTER TABLE

Table 5-6, "Base Address Registers Default Values", lists the Base Address Registers for logical devices which have

LPC memory access in the MEC1632.

• LPC Memory cycle access is controlled by LPC Memory Base Address Registers. LPC Memory BAR registers are

located in LDN Ch (LPC Interface) at AHB base address FF_3000h starting at offset 3C0h.

Note 5-3

The Mask and Frame fields of all logical devices are read-only except for 2h (ACPI EC Channel 0).

5.7

SERIRQ Interrupts

The MEC1632 can routes Logical Device interrupts onto SIRQ stream frames IRQ[0:15]. Routing is controlled by the

SIRQ Interrupt Configuration Registers. There is one SIRQ Interrupt Configuration Register for each accessible SIRQ

Frame (IRQ); all 16 registers are listed in Table 5-9, "SIRQ Interrupt Configuration Register Map". Each SIRQ Interrupt

Configuration Register controls a series of multiplexors which route to a single Logical Device interrupt as illustrated in

FIGURE 5-2: SIRQ Routing Internal Logical Devices on page 73. The format for each SIRQ Interrupt Configuration Reg-

ister is described in Table 5-10. Each Logical Device can have up to two LPC SERIRQ interrupts. When the MEC1632

is polled by the host, each SIRQ frame routes the level of the Logical Device interrupt (selected by the corresponding

SIRQ Interrupt Configuration Register) to the SIRQ stream. See

The SIRQ Interrupt Configuration Register The Host can access the Interrupt Configuration registers with 8-bit

accesses. The EC can access the Interrupt Configuration registers as four 32-bit registers, eight 16-bit registers or six-

teen 8-bit registers.

TABLE 5-8:

MEMORY BASE ADDRESS REGISTERS DEFAULT VALUES

Block

LDN

Memory Bar's

AHB Address

in CR Space (Hex)

Memory Bar's

LPC Offset in CR

Space (Hex)

Memory Bar's Default

Value (Hex)

Memory Bar

Decodes AHB

ADDR (HEX)

Mailbox

FF33C0h

C0h

0000_0000_0001h

FF0000

ACPIEC0

FF33C6h

C6h

0000_0062_0204h

FF0800

ACPIEC1

FF33CCh

CCh

0000_0062_0307h

FF0C00

ACPIEC2

FF33D2h

D2h

0000_0062_0407h

FF1000

ACPIEC3

FF33D8h

D8h

0000_0062_0507h

FF1400

Flash

FF33DEh

DEh

0000_0000_0E04h

FF3800

EMI

FF33E4h

E4h

0000_0000_100Fh

FF4000

Note:

Two Logical Devices cannot share a Serial IRQ.

Note:

An interrupt is deactivated by setting an entry in the SIRQ Interrupt Configuration Register Map to FFh,

which is the default reset value.

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