MEC1632 datasheet(81/636 Pages) MICROCHIP

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DS00001592B-page 81

MEC1632

6.2

Power, Clocks and Resets

6.2.1

POWER DOMAIN

This block is powered by VTR. Although the block is not powered by VCC, the block is also controlled by VCC_PWRGD.

When VCC_PWRGD is de-asserted, the LPC bus pins are placed in the same state they assume when VTR is off.

LAD[3:0] and SERIRQ are tri-stated, CLKRUN# is unpowered and LFRAME#, LRESET# and LPCPD# are gated high;

see Table 6-2, “LPC Bus Pin Behavior on Reset,” on page 83.The LPC block is also placed in a minimal power state.

See Section 7.1.1, "Power Configuration," on page 95 for details on power domains.

6.2.2

CLOCKS

LPC Logical Device Configuration Registers and LPC Logical Device EC-only Registers in this block are clocked by the

LPC Bus Clock. The LPC interface itself is clocked by the PCI_CLK clock input.

The clock rate of the LPC Bus Clock runs at the MCLK rate.

See Section 7.4, "Clock Generator," on page 98 for details on clocks.

6.2.3

RESETS

This block is affected by nSYS_RST, VCC Power Good and LPC RESET.

The assertion of nSYS_RST resets the LPC state machine and all registers to their default values. The AHB Master

state machine is also reset to its default value.

VCC Power Good going low resets the LPC state machine. The AHB Master interface that is part of the Host Interface

will go to its idle state. Any transaction that is active on the AHB Master when the VCC POR occurs will be terminated

in such a way that the AHB subsystem will not be locked up.

The assertion of LPC RESET# resets the LPC state machine but does not otherwise affect register values. An interrupt

to the EC will be generated on either edge of LRESET#. See Section 6.5, "Host Interrupts to EC," on page 84.

See Section 7.6, "Reset Interface," on page 124 for details on reset.

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