MEC1632 datasheet(53/636 Pages) MICROCHIP

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DS00001592B-page 53

MEC1632

3.7

Notes for Tables in this Chapter

3.8

Strapping Options

GPIO171 is used for the TAP Controller select strap (see Section 44.2.1, "TAP Controller Select Strap Option," on

page 580). If any of the MEC1632 JTAG TAP controllers are used, GPIO171 must only be configured as an output to

a VTR powered external function. GPIO171 may only be configured as an input when the JTAG TAP controllers are

not needed or when an external driver does not violate the Slave Select Timing as defined in Section 44.2.2, "Slave

Select Timing," on page 580.

GPIO166 is used for the UART_BOOT_STRAP option (see Section 42.4, "UART Boot Strap Option," on page 568.

See also Section 7.6.2, "Strap Options," on page 124.

Note 1

The nEC_SCI pin can be controlled by hardware and EC firmware. The nEC_SCI pin

can drive either the ACPI Run-time GPE Chipset input or the Wake GPE Chipset input.

Depending how the nEC_SCI pin is used, other ACPI-related SCI functions may be best

supplied by other general purpose outputs that can be configured as open-drain drivers.

Note 2

These pins require an external weak pull-up resistors of 10k-100k ohms.

Note 3

A pull-up is not needed on this BC-Link DATA pin as long as the voltage remains above the

logic-high threshold during the second turnaround cycle.

Note 4

The two pin debug port UART can be used by the Host or EC. This pin can be VCC protected

or not VCC portected under program control by the POWER bit in the Configuration Select

Note 5

When the JTAG_RST# pin is not asserted (logic'1'), the JTAG_TDI, JTAG_TDO, JTAG_CLK,

JTAG_TMS signal functions in the JTAG interface are unconditionally routed to the interface;

the Pin Control register for these pins has no effect. When the JTAG_RST# pin is asserted

(logic'0'), the JTAG_TDI, JTAG_TDO, JTAG_CLK, JTAG_TMS signal functions in the JTAG

interface are not routed to the interface and the Pin Control Register for these pins controls the

muxing. The pin control registers can not route the JTAG interface to the pins. System Board

Designer should terminate this pin in all functional state using jumpers and pull-up or pull

down resistors, etc .

Note 6

PS/2 ports ending with signal functions ending with "A" or "B" are muxed to a single

controller. Only one set of clock and data are intended to used at a time (either "A" or "B" not

both. The unused port segment should have its associated pin control register's, Mux Control

Field programmed away from the PS2 controller.

Note 7

The GPIO062 pin defaults to output 'low' on nSYS_RST to support the firmware controlled

RESETO# feature. RESETO# is not a GPIO alternate function; it is controlled by firmware as

a GPIO function.

Note 8

This pin has a GPIO signal for interrupt/wake-only signal functions.

Note 9

The LED pins do not have internal pull-downs.

Note 10

This pin is muxed with a BGPO signal that is configured by programming the Week Timer

Control register. When configured as the BGPO function the pad is powered by VBAT.

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