MEC1632 datasheet(62/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 62

 2012-2018 Microchip Technology Inc.

LPC Firmware Hub cycles and LPC Memory cycles are mapped into the address range 80_0000h to FF_FFFFh. This

range is mapped into the off-chip SPI Flash memory.

Because the EC does not require the mapping mechanism required for translating LPC Runtime Registers, Configura-

tion Registers and DMA channels, it accesses each 1KB frame uniformly. All Logical Devices located on the EC-only

AHB (those in the address range F0_0000h through F0_FFFFh) have a flat, 1KB frame.

For details on LPC address mapping to the MEC1632 address space, see Section 6.0, "Host Interface," on page 79.

4.4.3

AHB BUS ERRORS

AHB bus requests by both the Host, through the LPC bus, and the EC, can be terminated with an AHB bus error. The

handling of bus errors by the EC is described in the ARCompact™ Instruction Set Architecture: Programmer’s Refer-

ence

Bus errors may be caused by:

• EC I/O requests that lie outside the range of the Data Closely Coupled Memory, the EC SPB or the AHB-AHB

bridge

• I/O requests to either the Host SPB or the EC SPB that map to a non-existent Logical Device

• I/O requests to an invalid register address within a valid Logical Device on either the EC SPB or the Host SPB

4.5

Peripheral Buses (SPB)

The Peripheral Bus (SPB) is a byte-addressable bus with a 16-bit address space and a 32-bit data path. All accesses

must be aligned to the data-size boundaries. The SPB supports 32-bit, 16-bit and 8-bit accesses. All peripheral

accesses are 32-bits wide, so that if a peripheral cannot transfer more than 8 bits of a register in one I/O access, register

addresses should all be on 32-bit boundaries even though the upper bits (bits 31 through 8) are always zero. The SPB

will not assemble a 32-bit word out of multiple 8-bit accesses.

SPB transfers take two cycles, so that a read or write on the AHB to a register on the SPB will take a total of three cycles.

The SPB contains an 8-bit word address, four byte lane strobes and up to 64 logical device select strobes. Data on the

SPB read and write buses are always 32-bit aligned, with the byte strobes indicating which byte lane or lanes should be

active during a transaction. An SPB peripheral must steer bytes, based on the byte strobes, to the correct byte lane.

There are two SPB bridges forwarded to two SPB (busses):

LPC SPB

The LPC SPB address range is FF_0000h - FF_BFFFh and FF_C400h - FF_FFFFh.

EC SPB

The EC SPB address range is F0_0000h through F0_FFFFh

TABLE 4-5:

LPC TO MEC1632 ADDRESS MAPPING

Type of Access

Address Bit Mapping

LPC I/O Access

Runtime Registers

Address bits[9:8] = 00b

Address bits[23:10] set from map

No LPC Access

EC-only registers

Address bits[9:8] = 01b

LPC I/O Access through Configuration Access Port

Configuration Registers

Address bits[9:8] = 11b

Address bits[23:10] set from map

LPC DMA Access

Address bits[9:8] = 10b

Address bits[23:10] set from map

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