MEC1632 datasheet(83/636 Pages) MICROCHIP

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DS00001592B-page 83

MEC1632

6.3.1

LPC BUS INTERFACE

The MEC1632 communicates with the host over a Low Pin Count (LPC) interface. The LPC interface uses 3.3V signal-

ing. For detailed specifications, see the Intel Low Pin Count Specification and the PCI Local Bus Specification, Section

4.2.2.

The following cycle types are supported by the LPC Bus protocol.

• 8-bit I/O Read

• 8-bit I/O Write

• 8-bit Memory Reads

• 8-bit Memory Writes

LPC transactions that claimed by the MEC1632 require a minimum of two wait SYNCs on the LPC bus. The number of

SYNCs may be larger if the AHB bus is in use by the embedded controller, of if the data referenced by the host is not

present in a MEC1632 register. The MEC1632 always uses Long Wait SYNCs, rather than Short Wait SYNCs, when

responding to an LPC bus request.

The PCI_CLK input can run at 24MHz or 33MHz. When the PCI_CLK input is 24MHz the Hand shake bit in the EC Clock

Control Register must be set to a ‘1’ to capture LPC transactions properly. See Section 6.10.4, "EC Clock Control Reg-

ister," on page 92.

Table 6-2, "LPC Bus Pin Behavior on Reset", shows the behavior of LPC outputs and input/outputs under reset condi-

tions in accordance with the Intel Low Pin Count Specification and the PCI Local Bus. See Section 6.7, "LPC Clock Run

and LPC Power Down Behavior," on page 84 for LPC protocol dependent pin state transitions requirements.

6.3.2

LPC I/O CYCLES

LPC 8-bit I/O Read cycles and 8-bit I/O Write cycles are mapped directly to addresses in the MEC1632 AHB address

space. The mapping will be to the range FF_0000h through FF_FFFFh. For information on how addresses map between

the LPC bus and the MEC1632, see Section 4.0, "Bus Hierarchy," on page 55 and Section 5.0, "Logical Device Config-

uration," on page 63. For a list of all Configuration Registers accessible to the Host, see Section 5.0, "Logical Device

Configuration," on page 63.

6.3.3

LPC FIRMWARE HUB CYCLES

The MEC1632 does not support LPC Firmware Hub cycles on the LPC Bus.

6.3.4

LPC MEMORY CYCLES

The system host may use LPC memory cycles to access memory mapped registers and internal RAMs implemented in

this device. See the Intel® Low Pin Count (LPC) Interface Specification, v1.1, Section 5.1 for definition of LPC Memory

Cycles.

6.3.5

LPC DMA CYCLES

The MEC1632 does not support LPC DMA cycles.

6.4

LPC Bus Configuration

The mapping from LPC Bus cycles to AHB read/write cycles is managed by the LPC Logical Device. The mapping is

defined by a series of configuration registers which are defined in Section 5.0, "Logical Device Configuration," on

page 63, in Section 6.4, "LPC Bus Configuration," on page 83.

TABLE 6-2:

LPC BUS PIN BEHAVIOR ON RESET

Pins

nSYS_RST

VCC POR

LPCPD#

Asserted

LRESET#

Asserted

LAD[3:0]

Tri-state

Tri-State

SERIRQ

Tri-state

Tri-State

CLKRUN#

Tri-state

Tri-State

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