MEC1632 datasheet(67/636 Pages) MICROCHIP

67 / 636 page

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DS00001592B-page 67

MEC1632

Each BAR is 32 bits wide. The format of each BAR is summarized in Table 5-5, "Base Address Register Format". An

LPC I/O request is translated by the BAR into an 8-bit read or write transaction on the AHB bus. The 16-bit LPC I/O

address is translated into a 24-bit AHB address

The Base Address Register Table is itself part of the AHB address space. It resides in the Configuration quadrant of

Logical Device Ch, the LPC Interface.

MASK

These 7 bits are used to mask off address bits in the address match between an LPC I/O address and the Host Address

field of the BARs, as described in Section 5.6.3, "Mapping LPC I/O Addresses". A block of up to 128 8-bit registers can

be assigned to one base address.

FRAME

These 6 bits are used to specify a logical device frame number within a bus. This field is multiplied by 400h to provide

the frame address within the peripheral bus address. In the MEC1632 Frame values for frames corresponding to logical

devices that are not present on the MEC1632 are invalid.

VALID

If this bit is 1, the BAR is valid and will participate in LPC matches. If it is 0 this BAR is ignored

HOST_ADDRESS

These 16 bits are used to match LPC I/O addresses

5.6.3

MAPPING LPC I/O ADDRESSES

A Base Address Register will match an LPC I/O address, and thus the MEC1632 will claim the LPC bus cycle, if the

following relation holds:

(LPC Address & ~BAR.MASK) == (BAR.LPC_Address & ~BAR.MASK) && (BAR.Valid == 1)

If one of the BARs match, the LPC cycle will be claimed and the LPC request will be translated to an AHB address

according to the following formula:

AHB Address = FF_000h | (BAR.Frame<<10) | (LPC_Address & BAR.MASK)

The formula is illustrated in Figure 5-1, "LPC BAR Mapping".

Note:

Software should that insure that no two BARs map the same LPC I/O address. If two BARs do map to the

same address, the BAR_Conflict bit in the Host Bus Error Register is set when an LPC access targeting

the BARConflict address. An EC interrupt can be generated.

TABLE 5-5:

BASE ADDRESS REGISTER FORMAT

BYTE3 BIT

D31

D30

D29

D28

D27

D26

D25

D24

BIT NAME

LPC Host Address, most significant bits

BYTE2 BIT

D23

D22

D21

D20

D19

D18

D17

D16

BIT NAME

LPC Host Address, least significant bits

BYTE1 BIT

D15

D14

D13

D12

D11

D10

BIT NAME

Valid

Reserved

Frame

BYTE0 BIT

D7D6D5D4D3D2D1D0

BIT NAME

Reserved

Mask

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