LSM6DSO32 datasheet(93/153 Pages) STMICROELECTRONICS

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LSM6DSO32

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9.51

I3C_BUS_AVB (62h)

I3C_BUS_AVB register (r/w)

Table 139. I3C_BUS_AVB register description

9.52

INTERNAL_FREQ_FINE (63h)

Internal frequency register (r)

Table 141. INTERNAL_FREQ_FINE register description

9.53

X_OFS_USR (73h)

Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR

offset register is internally subtracted from the acceleration value measured on the X-axis.

Table 138. I3C_BUS_AVB register

0(1)

1. This bit must be set to '0' for the correct operation of the device.

0(1)

I3C_Bus_

Avb_Sel1

I3C_Bus_

Avb_Sel0

0(1)

PD_DIS_

INT1

PD_DIS_INT1

This bit allows disabling the INT1 pull-down.

(0: Pull-down on INT1 enabled (pull-down is effectively connected only when no

interrupts are routed to the INT1 pin or when I3C dynamic address is assigned);

1: Pull-down on INT1 disabled (pull-down not connected)

I3C_Bus_Avb_

Sel[1:0]

These bits are used to select the bus available time when I3C IBI is used.

Default value: 00

(00: bus available time equal to 50 μsec (default);

01: bus available time equal to 2 μsec;

10: bus available time equal to 1 msec;

11: bus available time equal to 25 msec)

Table 140. INTERNAL_FREQ_FINE register

FREQ_

FINE7

FREQ_

FINE6

FREQ_

FINE5

FREQ_

FINE4

FREQ_

FINE3

FREQ_

FINE2

FREQ_

FINE1

FREQ_

FINE0

FREQ_FINE[7:0]

Difference in percentage of the effective ODR (and Timestamp Rate) with

respect to the typical. Step: 0.15%. 8-bit format, 2's complement.

Table 142. X_OFS_USR register

X_OFS_

USR_7

X_OFS_

USR_6

X_OFS_

USR_5

X_OFS_

USR_4

X_OFS_

USR_3

X_OFS_

USR_2

X_OFS_

USR_1

X_OFS_

USR_0

Table 143. X_OFS_USR register description

X_OFS_USR_

[7:0]

Accelerometer X-axis user offset correction expressed in two’s complement,

weight depends on USR_OFF_W in CTRL6_C (15h). The value must be in the

range [-127 127].

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