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STM32WB15CC датащи(PDF) 115 Page - STMicroelectronics |
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STM32WB15CC датащи(HTML) 115 Page - STMicroelectronics |
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115 / 127 page ![]() DS13258 Rev 4 115/127 STM32WB15CC Electrical characteristics 115 conditions summarized in Table 21: General operating conditions. with the following configuration: Capacitive load C = 30 pF Measurement points are set at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.16 for more details on the input/output alternate function characteristics (CK, SD, WS). Table 81. JTAG characteristics Symbol Parameter Conditions Min Typ Max Unit 1/tc(TCK) TCK clock frequency 2.7 < VDD < 3.6 V - - 29 MHz 1.71 < VDD < 3.6 V - - 21 tisu(TMS) TMS input setup time - 2.5 - - ns tih(TMS) TMS input hold time - 2.0 - - tisu(TDI) TDI input setup time - 2.0 - - tih(TDI) TDI input hold time - 2.0 - - tov(TDO) TDO output valid time 2.7 < VDD < 3.6 V - 13.5 16.5 1.71 < VDD < 3.6 V - 13.5 23 toh(TDO) TDO output hold time - 11 - - Table 82. SWD characteristics Symbol Parameter Conditions Min Typ Max Unit 1/tc(SWCLK) SWCLK clock frequency 2.7 < VDD < 3.6 V - - 55 MHz 1.71 < VDD < 3.6 V - - 35 tisu(TMS) SWDIO input setup time - 2.5 - - ns tih(TMS) SWDIO input hold time - 2.0 - - tov(TDO) SWDIO output valid time 2.7 < VDD < 3.6 V - 16 18 1.71 < VDD < 3.6 V - 16 28 toh(TDO) SWDIO output hold time - 13 - - |
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