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STM32WB15CC датащи(PDF) 113 Page - STMicroelectronics |
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STM32WB15CC датащи(HTML) 113 Page - STMicroelectronics |
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113 / 127 page ![]() DS13258 Rev 4 113/127 STM32WB15CC Electrical characteristics 115 Figure 24. SPI timing diagram - Slave mode and CPHA = 0 tsu(MI) Data input setup time Master mode 6.5 - - ns tsu(SI) Slave mode 1.5 - - th(MI) Data input hold time Master mode 4.5 - - th(SI) Slave mode 1.5 - - ta(SO) Data output access time Slave mode 9- 34 tdis(SO) Data output disable time 9 - 16 tv(SO) Data output valid time Slave mode 2.7 < VDD < 3.6 V - 10.5 13 Slave mode 1.71 < VDD < 3.6 V - 10.5 20.5 tv(MO) Master mode (after enable edge) - 2.5 3.0 th(SO) Data output hold time Slave mode (after enable edge) 8 - - th(MO) Master mode (after enable edge) 1.0 - - 1. Evaluated by characterization, not tested in production. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50 %. Table 80. SPI characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit (SI) MSB IN BIT1 IN LSB IN BIT6 OUT MSB OUT LSB OUT NSS input MOSI INPUT MISO OUTPUT (SI) |
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