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STM32WB15CC датащи(PDF) 83 Page - STMicroelectronics

номер детали STM32WB15CC
подробное описание детали  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 radio solution
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STM32WB15CC датащи(HTML) 83 Page - STMicroelectronics

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DS13258 Rev 4
83/127
STM32WB15CC
Electrical characteristics
115
6.3.8
Wakeup time from Low-power modes and voltage scaling
transition times
The wakeup times given in Table 44 are the latency between the event and the execution of
the first user instruction.
The device goes in Low-power mode after the WFE (Wait For Event) instruction.
APB1
RTCA
0.940
0.875
µA/MHz
I2C1 independent clock domain
1.95
3.90
I2C1 clock domain
3.75
4.10
LPTIM1 independent clock domain
1.95
2.90
LPTIM1 clock domain
3.45
3.60
TIM2
4.55
4.00
LPTIM2 clock domain
3.45
3.70
LPTIM2 independent clock domain
1.95
2.90
WWDG
0.350
0.625
LPUART1 independent clock domain
2.60
3.70
LPUART1 clock domain
4.55
4.05
All APB1 peripherals
15.5
16.0
APB2
AHB to APB2(3)
0.900
1.10
TIM1
6.25
6.10
USART1 independent clock domain
3.05
6.50
USART1 clock domain
6.25
5.50
SPI1
1.25
1.05
ADC1 independent clock domain
0.940
0.600
ADC1 clock domain
0.780
0.600
All APB2 on
14.5
15.5
ALL
51.5
48.0
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. GPIOs consumption during read and write accesses.
3. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2.
Table 43. Peripheral current consumption (continued)
Peripheral
Run
Low-power
run and Sleep
Unit



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