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STM32WB15CC датащи(PDF) 114 Page - STMicroelectronics |
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STM32WB15CC датащи(HTML) 114 Page - STMicroelectronics |
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114 / 127 page ![]() Electrical characteristics STM32WB15CC 114/127 DS13258 Rev 4 Figure 25. SPI timing diagram - Slave mode and CPHA = 1 1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 26. SPI timing diagram - Master mode 1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD. JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 81 and Table 82 are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage ai14135b NSS input tSU(NSS) tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) MISO OUTPUT MOSI INPUT tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB OUT LSB IN BIT 1 IN ai14136c CPHA= 0 MOSI OUTPUT MISO INP UT CPHA= 0 LSB OUT LSB IN CPOL=0 CPOL=1 B I T1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) MSB IN BIT6 IN MSB OUT |
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