STM32WB15CC datasheet(26/127 Pages) STMICROELECTRONICS

26 / 127 page

Functional overview

STM32WB15CC

26/127

DS13258 Rev 4

By default, the microcontroller is in Run mode, after a system or a power on Reset. It is up to

the user to select one of the low-power modes described below:



Sleep

In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem,

continue to operate and can wake up the CPU when an interrupt/event occurs.



Low-power run

This mode is achieved with VCORE supplied by the low-power regulator to minimize

the regulator operating current. The code can be executed from SRAM or from the

Flash memory, and the CPU1 frequency is limited to 2 MHz. The peripherals with

independent clock can be clocked by HSI16. The RF subsystem is not available in this

mode and must be OFF.



Low-power sleep

This mode is entered from the low-power run mode. Only the CPU1 clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the



low-power run mode. The RF subsystem is not available in this mode and must be

OFF.



Stop 0 and Stop 1

Stop modes achieve the lowest power consumption while retaining the content of all

the SRAM and registers. The LSE (or LSI) is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop modes

to detect their wakeup condition.

Two modes are available: Stop 0 and Stop 1.

Stop 1 offers several active peripherals and wakeup sources. In Stop 0 mode the main

regulator remains ON, allowing a very fast wakeup time but with higher consumption.

In these modes the RF subsystem can wait for incoming events in all Stop modes.

The system clock when exiting from Stop 0 or Stop1 modes can be either MSI up to

48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem is used the exits

must be set to HSI16 only.



Standby

The Standby mode is used to achieve the lowest power consumption with BOR. The

internal regulator is switched off so that the VCORE domain is powered off.

The RTC can remain active (Standby mode with RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with

internal pull-up, internal pull-down or floating.

After entering Standby mode, register content is lost except for registers in the Backup

domain and Standby circuitry. Optionally, SRAMs can be retained in Standby mode,

supplied by the low-power regulator (Standby with 48 KB SRAM retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,

periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

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