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STM32WB15CC датащи(PDF) 108 Page - STMicroelectronics |
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STM32WB15CC датащи(HTML) 108 Page - STMicroelectronics |
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108 / 127 page ![]() Electrical characteristics STM32WB15CC 108/127 DS13258 Rev 4 Figure 23. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function 1. Refer to Table 69: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 64: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades the conversion accuracy. To remedy this fADC must be reduced. 3. Refer to Table 64: I/O static characteristics for the values of Ilkg. 4. Refer to Figure 13: Power supply scheme. General PCB design guidelines Power supply decoupling has to be performed as shown in Figure 13: Power supply scheme. The 10 nF capacitor must be ceramic (good quality), placed as close as possible to the chip. 6.3.20 Comparator characteristics MSv67871V3 Sample-and-hold ADC converter Converter Cparasitic (2) Ilkg (3) CADC VDDA (4) RAIN (1) VAIN RADC VREF+ (4) VSSA I/O analog switch Sampling switch with multiplexing VSS VSS Table 72. COMP characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage - 1.62 - 3.6 V VIN Comparator input voltage range -0 - VDDA VBG(2) Scaler input voltage - VREFINT VSC Scaler offset voltage - - ±5 ±10 mV IDDA(SCALER) Scaler static consumption from VDDA BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA tSTART_SCALER Scaler startup time - - 100 200 µs tSTART Comparator startup time to reach propagation delay specification High-speed mode VDDA ≥ 2.7 V - - 5 µs VDDA < 2.7 V - - 7 Medium mode VDDA ≥ 2.7 V - - 15 VDDA < 2.7 V - - 25 Ultra-low-power mode - - 40 |
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