ECE1200 datasheet(17/87 Pages) MICROCHIP

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DS00003093C Draft-page 17

ECE1200

3.4.2

POWER GOOD SIGNALS

The Power Good timing is defined in the Section 9.5, "Voltage Sequencing and Power Good Timing," on page70.

3.4.3

SYSTEM POWER SEQUENCING

See Section 9.7, "System Power State Transition Diagrams," on page 70 for behavior under system power state

changes.

VTR_CORE_18

1.8V

1.8V Core Logic Power Supply

This supply is used to power the internal logic.

It is to be connected to the 1.8V “Always-on” /

“Suspend” / ”S5” supply rails in system. It is on its

own pin in order to allow isolation and decoupling

from the VTR_18 pin, otherwise it is identical.

There is no need to connect it to a deeper power

well, such as the Deep Sleep Well, even if that is

what powers the downstream LPC device(s).

This supply must be on prior to the RESETI# sig-

nal being deasserted (system RSMRST#).

Pin Interface

Note:

The VTR_33 supply must always be at or above the voltage on the 1.8V supply pins, including during

power-on and power-off sequences, otherwise excessive current may occur. VTR_18 and VTR_CORE_18

must turn on at the same time as, or after, the VTR_33 supply is powered. VTR_18 and VTR_CORE_18

must come from the same system well, rising and falling together.

TABLE 3-2:

POWER GOOD SIGNAL DEFINITIONS

Power Good

Signal

Description

Source

RESETI#

This is the Power-On Reset (POR) input for all

the VTR input wells.

RESETI# is to be held low initially, and set high

following a delay after all of the VTR power pins

have reached their valid levels. RESETI# is to

be pulled low as soon as either of these voltages

drop below this threshold. At no time may this

signal glitch during power transitions.

It is strongly recommended that this pin be con-

nected to the system RSMRST# signal, which

will assure these needs.

LPC_EN

This input is used to indicate when the Main (S0)

power rail voltages are on and stable.

LPC_EN indicates to the ECE1200 when the

downstream resources (LPC, Serial IRQ and

CLKRUN#) are powered. The low state prevents

these pins from driving high, avoiding backdrive

of the other components. At no time may this

signal glitch during power transitions.

It is strongly recommended that this pin be con-

nected to the system PCH_PWROK signal,

which will assure these needs.

TABLE 3-1:

POWER SOURCE DEFINITIONS (CONTINUED)

Power Well

Nominal

Voltage

Description

Source

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