ECE1200 datasheet(29/87 Pages) MICROCHIP

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DS00003093C Draft-page 29

ECE1200

5.6

The registers associated with eSPI itself are only the eSPI Configuration Registers. They are accessed only for initial-

ization of eSPI communication parameters, by Chipset hardware after removal of the eSPI_RESET# signal. See Section

5.8, "eSPI Configuration Registers," on page 30 for details of these special registers.

Other registers, used for controlling the Bridging functionality between eSPI and LPC, are described in Section 6.0,

"Device Register Set and Initialization," on page 33.

5.7

Description

5.7.1

OPERATING FREQUENCY

The part supports standard eSPI specifications up to the 50MHz operating frequency. It does not, however, enforce a

limit to the Host Chipset, which remains in full control of the frequency selection. See the Intel Compatibility Specification

document listed in Section 5.2, "References" for the “Soft-Straps” that declare this for the system.

Any additional eSPI Slave may have its own independent frequency setting, including the maximum 66MHz, and its traf-

fic will have no effect on this device.

5.7.2

PERIPHERAL CHANNEL SUBSET

The eSPI Peripheral Channel supports I/O and Memory traffic initiated by the Host System. It does not support eSPI

Memory Mastering emulation to Host DRAM, nor the associated LTR command.

It therefore does not attempt to re-create legacy LPC DMA or Mastering.

5.7.3

VIRTUAL WIRE CHANNEL SUBSET

As referenced to the Intel Compatibility Specification document listed in Section 5.2, "References", a subset of Virtual

Wires is implemented as shown in Table 5-4. “RFU” represents a Virtual Wire that is implemented for future use only.

In Table 5-4, the following notations are used:

• IDX is the Virtual Wire Index number for the group of 4 Virtual Wires.

• Dir is the Virtual Wire direction for that Index: “Dn” (Down) is Master to Slave, “Up” is Slave to Master.

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