ECE1200 datasheet(74/87 Pages) MICROCHIP

74 / 87 page

ECE1200

DS00003093C Draft-page 74

 2018-2021 Microchip Technology Inc.

9.7.4

TEARDOWN FROM S0 TO S5, LPC CLOCKS RUNNING

FIGURE 9-4:

TEARDOWN FROM S0 TO S5, LPC CLOCKS RUNNING

LPC_EN

(pin in)

3.3V

ASYNCH

Stop

SUS_STAT#

(VWire Down

to pin out)

3.3V

LAD[3:0],

SERIRQ

3.3V

Running

3.3V

CLKRUN#

as PCH_PWROK, via SLP_S3# (invisible)

Running

SUSCLK

32KHz

3.3V

LPC_CLK[1:0]

3.3V

SLP_EN bit

(invisible, in PCH)

HOST_RESET_WARN

(VWire Down)

Transition below S0

HOST_RESET_ACK

(VWire Up if CS0#,

pin out if CS1#)

Transmitted as VWire edge up if Primary.

Presented on pin instead if Secondary.

Kept Running

(CLKRUN bits bypassed)

Running

(CLKRUN bits reset)

Idle,

float

PLTRST#

(pin in)

3.3V

Would be

cleared here,

but no edge in

this case.

from PCH

Reset internally, float

Sleep

S3 to S5

Running

eSPI Bus

1.8V

Bypass

CLKRUN bits.

Driven low

Notes in red indicate aspects unique to this scenario.

These edges happen only when a sub-S0

Sleep or Shutdown is being performed.

Driven low

Running

(LPC / SERIRQ Traffic)

Forced low

eSPI Requests done but an LPC

Mem Write may be in progress.

Wait for LPC done. No error report.

Issue Continuous Mode frame on

SERIRQ and wait for it to end.

Then send ACK edge if on CS0#.

Idle, potentially

driven

LFRAME#

3.3V

Running

(Host CPU reset)

Idle, driven

inactive

Idle,

driven

low.

Initially low

205us min

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