ECE1200 datasheet(24/87 Pages) MICROCHIP

24 / 87 page

ECE1200

DS00003093C Draft-page 24

 2018-2021 Microchip Technology Inc.

The IOCHK Posted Error Handling Register, Section 6.9.10, on page 42 defines the action to be taken if the IOCHK#

input is activated during the Wait phase of a Posted LPC transfer (Memory Write).

These situations above do not by themselves terminate the LPC transfer, and the peripheral device must terminate the

transfer itself (by a SYNC code other than Wait).

The IOCHK Idle Error Handling Register, Section 6.9.7, on page 41 defines the action to be taken if the IOCHK# input

is activated outside of an LPC transfer.

4.7.1

ENABLING THE SERIAL IRQ FUNCTION

The Serial IRQ feature is disabled by default, and must be enabled. To enable Serial IRQ channel the host must initialize

it as described in Section 6.8.4, "Set Up Serial IRQ," on page 37. This may be done either before or after LPC sources

have been initialized.

4.8

Error Reporting and Logging Registers

4.8.1

VIRTUAL WIRE STATES AND CLEARING

Four eSPI Virtual Wires are available for reporting LPC errors or the IOCHK# event, as programmed in the various Error

Handling registers mentioned above. Each Virtual Wire, once posted and signaled to the Chipset, can be polled and

cleared by register accesses. The Virtual Wires are:

• ERROR_FATAL

• ERROR_NONFATAL

•SMI#

•SCI#

The Virtual Wires ERROR_FATAL and ERROR_NONFATAL are polled and cleared in the eSPI Virtual Wire Errors Reg-

ister, Section 6.9.11, on page 43. They are also cleared by an eSPI_RESET# event.

The Virtual Wires SMI# and SCI# are polled and cleared in the eSPI Virtual Wire Error Events Register, Section 6.9.12,

on page 43. These Virtual Wires are cleared by PLTRST# events as well as eSPI_RESET# events (eSPI_RESET# low

asserts PLTRST# low as well).

The SMI# Virtual Wire is not recorded in the ECE1200 if it is the result of a Serial IRQ report. In that case, it will be

recorded in the originating device, and can be polled and cleared there, propagating through the ECE1200 as it changes

state on the Serial IRQ port. A PLTRST# event will clear it in the ECE1200, as well as at the originating device.

4.8.2

LPC CYCLE ERROR LOGGING

The various error conditions occurring during an LPC transfer are logged as individual bits in two registers:

•The LPC Error Log Non-Posted Register, Section 6.11.8, on page 56 holds errors detected in Non-Posted trans-

fers.

•The LPC Error Log Posted Register, Section 6.11.9, on page 56 holds errors detected in Posted transfers.

In addition, the address and type of LPC access are captured on each error:

•The Error Cycle Attributes Register, Section 6.11.14, on page 57 holds the type of access: Read vs.Write and I/O

vs. Memory.

• The four Error Cycle Address registers, starting at Section 6.11.10, on page 57, hold the address captured from

the LPC bus on an error. I/O addresses load only the low-order two bytes of the address; Memory addresses load

all four bytes.

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