ECE1200 datasheet(79/87 Pages) MICROCHIP

номер детали	ECE1200

подробное описание детали	eSPI to LPC Bridge

PDF	87 Pages

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производитель	MICROCHIP [Microchip Technology]

домашняя страница	http://www.microchip.com

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 2018-2021 Microchip Technology Inc.

DS00003093C Draft-page 79

ECE1200

9.7.9

WAKE FROM S0IX STATE VIA CLKRUN# AND SERIRQ

FIGURE 9-9:

WAKE FROM S0IX STATE VIA CLKRUN# AND SERIRQ

LPC_EN

(pin in)

3.3V

SUS_STAT#

(VWire Down

to pin out)

3.3V

1.8V

Running

3.3V

CLKRUN#

System must make PLTRST# fall first.

Idle

Running

SUSCLK

32KHz

3.3V

LPC Clock Gates

3.3V

Running

HOST_C10

(VWire Down)

on PLTRST#

reset domain

Oscillator Enable

(Internal)

HOST_RESET_WARN

(VWire Down)

PLTRST#

(pin in)

3.3V

Running

48MHz

Oscillator

(Internal)

LFRAME#

LAD[3:0]

3.3V

Running

Idle

Off

Other signals, (FYI)

S0ix

(Rising would have awakened device by eSPI activity, then forced CLKRUN# low.)

(Falling would have awakened device by eSPI activity.)

eSPI_CS#

pin. eSPI bus

Oscillator Locked

(Internal)

No Lock

Locked

Eventually cleared

by Chipset.

LPC accesses

SERIRQ from

Peripheral

(Quiet Mode)

3.3V

Run

Idle

1.8V

Running

eSPI_ALERT#

event pin

(IO[1] or

dedicated)

VWire(s) from

SERIRQ packet

Running Quiet Mode traffic

Pulled low by

LPC peripheral

Kept low by bus,

IRQ activity.

PUT_VWIRE

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