ECE1200 datasheet(76/87 Pages) MICROCHIP

76 / 87 page

ECE1200

DS00003093C Draft-page 76

 2018-2021 Microchip Technology Inc.

9.7.6

TEARDOWN FROM S5 TO VTR OFF

FIGURE 9-6:

TEARDOWN FROM S5 TO VTR OFF

LPC_EN

(pin in)

3.3V

eSPI_RESET#

(pin in)

3.3V

as System PCH_PWROK

PLTRST#

(pin in)

Sleep S3 to S5

(transitions

not relevant)

3.3V

Driven low

RESETI#

(pin in)

3.3V

VTR_xx

(power)

3.3V, 1.8V (valid)

as System RSMRST#

400ns

min

OOB_RESET_WARN

(VWire Down)

OOB_RESET_ACK

(VWire Up)

Mirrors WARN.

Edge not

transmitted:

mutual reset.

If BOOT_DONE = 0 do not transmit as a VWire.

Host receives ACK from the other eSPI slave.

If BOOT_DONE = 1

SUSWARN#

(VWire Down to

output pin)

SUSACK#

(VWire Up from

input pin)

do not transmit as a VWire.

Host receives ACK from the other eSPI slave.

If BOOT_DONE = 0 ignore input pin;

If BOOT_DONE = 1

System wraps from SUSWARN# pin,

either directly or with delay for power mgmt.

Permission to

cycle VTR off.

(Removed

on ACK=1)

SUS_PWRDN_ACK

(VWire Down to

output pin)

SUSPWRDNACK to output pin:

status to system; no internal use.

(Non-DSW alternative to

SUSWARN# / SUSACK# handshake)

Running

SUSCLK

32KHz

3.3V

Running

eSPI Bus

1.8V

3.3V

(DSW feature: May not be exercised in all systems.)

Final

Transition

to VTR Off

Handshake Sequences

before VTR Off

Running

(non-DSW)

(DSW)

If BOOT_DONE = 0, this signal does not appear:

pin is HOST_RST_ACK instead.

ACK follows all WARN edges,

at all times, and will end low

in this specific sequence.

Reset event

(typ. no edges)

(DSW)

(non-DSW)

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