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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FXLS8974CF датащи(PDF) 77 Page - NXP Semiconductors |
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FXLS8974CF датащи(HTML) 77 Page - NXP Semiconductors |
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77 / 96 page  NXP Semiconductors FXLS8974CF 3-Axis Low-g Accelerometer The scaling for this register is always the same as the selected FSR sensitivity. See Section 9 for the sensitivity values corresponding to each of the selectable FSRs. Bit 7 6 5 4 3 2 1 0 Name — — — — SDCD_UTHS[11:8] Reset (BT_MODE = GND) 0 0 0 0 0 0 0 0 Reset (BT_MODE = VDD) 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 114. SDCD_UTHS_MSB register (address 36h) bit allocation Field Description 3 to 0 SDCD_UTHS[11:8] MSB (nibble) of the signed 12-bit 2's complement upper-threshold value Table 115. SDCD_UTHS_MSB register (address 36h) bit description 15.32 SELF_TEST_CONFIG1 register (address 37h) Bit 7 6 5 4 3 2 1 0 Name — — — ST_IDLE[4:0] Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 116. SELF_TEST_CONFIG1 register (address 37h) bit allocation Field Description 4 to 0 ST_IDLE Self-Test Idle phase duration: The value contained in ST_IDLE determines the Self-Test Idle phase duration per Equation 3. (3) Table 117. SELF_TEST_CONFIG1 register (address 37h) bit description 15.33 SELF_TEST_CONFIG2 register (address 38h) Bit 7 6 5 4 3 2 1 0 Name — — — — ST_DEC[3:0] Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 118. SELF_TEST_CONFIG2 register (address 38h) bit allocation FXLS8974CF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Objective data sheet Rev. 1 — 27 April 2021 77 / 96 |
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