FXLS8974CF datasheet(26/96 Pages) NXP

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NXP Semiconductors

FXLS8974CF

3-Axis Low-g Accelerometer

Operating mode

VDD min

VDD pin level

BOOT

TBOOT1

Edge triggered wakeup on SPI_CS_B/WAKE_UP line

aaa-040848

TPULSE - BOOT1

INT/MOT_DET

BOOT

OFF

STANDBY

Hibernate

STANDBY

SENS_CONFIG1

[ACTIVE] = 1

SENS_CONFIG5

[HIBERNATE_EN] = 1

SPI serial

command

SPI_CS_B

/WAKE_UP

ACTIVE (WAKE)

TPULSE - BOOT1

Figure 16. BOOT1 sequence (BT_MODE = GND)

Protocol

phase

Description

VDD supply is not present (VDD < VDDmin); MCU and FXLS8974CF are both off; all IO pins are floating/high-z.

VDD ≥ VDDmin; MCU and FXLS8974CF are turned on; FXLS8974CF performs the BOOT sequence and

provides the BOOT_OUT output pulse for TPULSE-BOOT1 ms.

FXLS8974CF enters standby mode directly after the BOOT sequence.

When the MCU sends a serial command to set

SENS_CONFIG5[HIBERNATE_EN] bit to 1, FXLS8974CF

enters Hibernate mode. NOTE: The device enters into Hibernate mode 1us (typ) after the SPI_CS_B line is

de-asserted for the corresponding HIBERNATE_EN serial command.

To wake up the device from Hibernate mode, the MCU toggles the SPI_CS_B/WAKE UP pin (see TFLT-

WAKE_UP deglitch filter time for transition out of Hibernate mode); FXLS8974CF performs the BOOT sequence

and provides the BOOT_OUT output pulse for TPULSE-BOOT1 ms.

FXLS8974CF enters standby mode directly after the BOOT sequence.

When the MCU sends a serial command to set

SENS_ CONFIG1[ACTIVE] bit to 1, FXLS8974CF enters

active mode.

Table 19. BOOT1 sequence description (BT_MODE = GND)

15 Register descriptions

Auto-increment Address

Name

Type

Address

F_READ = 0

F_READ = 1

Default

Values

BT_MODE =

GND/[VDD]

Comment

INT_STATUS [1] [2]

00h

01h/02h/04h/06h/

08h/0Ch/0Eh/10h

01h

Interrupt and system status event flags.

TEMP_OUT [1]

01h

02h/04h/06h/08h/ 0Ch/0Eh/10h

—

Temperature output data – temp_out[7:0]. When

SENS_CONFIG2[AINC_TEMP] = 0 the auto-

increment mechanism skips this register.

VECM_LSB [1] [3]

02h

03h

04h/06h/08h/

0Ch/0Eh/10h

—

12-bit unsigned vector magnitude LSB/MSB:

VECM[7:0] (LSB) when

SENS_CONFIG2[LE_BE]

= 0, and VECM[11:4] (MSB) when

SENS_

CONFIG2[LE_BE] = 1. This register is skipped over

by the auto-increment mechanism when

SENS_

CONFIG5[VECM_EN] = 0.

Table 20. Register address map

FXLS8974CF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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