FXLS8974CF datasheet(45/96 Pages) NXP

45 / 96 page

NXP Semiconductors

FXLS8974CF

3-Axis Low-g Accelerometer

Field

Description

5 to 4

SLEEP_PM[1:0]

SLEEP power mode selection

00b: Low-power mode is selected;

SENS_CONFIG3[3:0] bits are interpreted as SLEEP_ODR[3:0]

and sets the ODR and decimation factor as per Table 52.

01b: High performance mode is selected;

SENS_CONFIG3[3:0] bits are interpreted as

SLEEP_ODR[3:0] and set the ODR and decimation factor as per Table 53.

1xb: Flexible performance mode is selected;

SENS_CONFIG3[3:0] bits are interpreted as

SLEEP_DEC[3:0], which sets the measurement decimation factor. The effective ODR (and

measurement current) is determined by the combination of the decimation factor and the 12-bit

measurement idle time programmed in the

SLEEP_IDLE_MSB and SLEEP_IDLE_LSB registers.

See Table 54 for the selectable decimation factors.

Note: In motion detection mode with BT_MODE=VDD, use of HPM or FPM mode is not advised. Only

the default LPM mode should be used.

LE_BE

Little/Big-endian output mode selection

0: Little-endian output mode is selected; the output data LSBs are stored at the lower logical address

and the MSBs (nibbles) are right-justified.

1: Big-endian output mode is selected; the output data MSBs are stored at the lower logical address

and the LSBs (nibbles) are left justified.

Note: The output data format selection applies only to the data read from the OUT_X/Y/Z, VECM,

and

BUF_X/Y/Z registers. All other multi-byte fields within the device are fixed in little-endian right

justified format.

AINC_TEMP

Temperature output data auto-increment control

0 (default):

TEMP_OUT register content is not included in auto-increment address range.

TEMP_OUT register content is included in auto-increment address range.

F_READ

Fast-read mode selection

When this bit is set, the output data format is limited to the most significant byte of the 12-bit sample.

The MSB data is always stored in the lower address, regardless of the setting made in

SENS_

CONFIG1[LE_BE]. The auto-increment address pointer automatically skips over the higher address

for each axis' sample when performing a burst read operation of the current output data or buffered

data when the F_READ bit is set.

0: Normal read mode

1: Fast-read mode

Table 50. SENS_CONFIG2 register (address 16h) bit description...continued

15.13 SENS_CONFIG3 register (address 17h)

The SENS_CONFIG3 register is used to set the WAKE and SLEEP ODRs when

operating in low-power mode or High Performance Mode, and the decimation factor for

WAKE and SLEEP modes in Flexible Power Mode.

Notes:

• In motion detection mode with BT_MODE=VDD, use of HPM or FPM mode is not

advised. Only the default LPM mode should be used.

• When BT_MODE=VDD, maximum recommended ODR is 100 Hz. When the data

ready interrupt is enabled, the interrupt line (INT1) will pulse low for TPULSE-MOT

seconds (

5 ms typ) for every ODR period. Therefore, for higher ODRs, the host does

not observe DRDY interrupt pulse at every ODR period.

FXLS8974CF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

45 / 96

FXLS8974CF датащи(PDF) 45 Page - NXP Semiconductors

FXLS8974CF датащи(HTML) 45 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

датащи скачать

ссылки URL