FXLS8974CF datasheet(30/96 Pages) NXP

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NXP Semiconductors

FXLS8974CF

3-Axis Low-g Accelerometer

Auto-increment Address

Name

Type

Address

F_READ = 0

F_READ = 1

Default

Values

BT_MODE =

GND/[VDD]

Comment

reserved register 12

R/W

39h

3Ah

00h

Factory reserved register; do not modify

reserved register 13[1]

3Ah

00h

—

Factory reserved register

Table 20. Register address map...continued

[1]

Register contents are preserved when a transition from ACTIVE to STANDBY mode occurs. All register contents are lost when a transition from Hibernate

mode or a POR/BOR event occurs.

[2]

[3]

The byte order and L/R justification of these registers is user programmable between little-endian right justified and big-endian (left justified) modes. The

default mode is little-endian, right justified. The byte order and justification is controlled by

SENS_CONFIG3[LE_BE].

[4]

The output data buffer contents become obsolete whenever a transition from STANDBY-to-ACTIVE or STANDBY-to-EXT_TRIG modes occurs.

[5]

SENS_CONFIG1[ACTIVE], SENS_

CONFIG1[RST] and BUF_CONFIG1[BUF_FLUSH] bits that may be set at any time in STANDBY, ACTIVE, or EXT_TRIG modes. The ACTIVE bit state

cannot be modified while in EXT_TRIG operating mode.

15.1 INT_STATUS register (address 00h)

Bit

Name

SRC_DRDY SRC_OVF

SRC_BUF

SRC_

SDCD_OT

SRC_

SDCD_WT

SRC_

ORIENT

SRC_ASLP SRC_BOOT

Reset

Access

Table 21. INT_STATUS register (address 00h) bit allocation

Field

Description

SRC_DRDY

Output data-ready event flag

0: A new set of XYZ acceleration and temperature data is not available.

1: A new set of XYZ acceleration and temperature data is available

Notes:

• The SRC_DRDY flag is cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are

read.

• Whenever BUF_CONFIG1[BUF_MODE1:0]] > 00b (buffer enabled), SRC_DRDY is held at logic '0'.

• When BT_MODE=GND, SRC_DRDY bit and the signaled interrupt are cleared whenever one or

more of the VECM, and OUT_X/Y/Z registers are read.

• When BT_MODE=VDD, SRC_DRDY bit is cleared whenever one or more of the VECM, and

OUT_X/Y/Z registers are read. However the data ready interrupt is signaled for TPULSE-MOT

seconds (5 ms typ) and it clears itself automatically. The current data ready interrupt pulse is

terminated when the device transitions into STANDBY mode before its completion and therefore

may not span for entire TPULSE-MOT seconds.

SRC_OVF

Output data overflow event flag

0: No overflow condition detected.

1: A new set of XYZ acceleration and temperature output data latches into

OUT_X/Y/Z and TEMP_

OUT registers before the previous set is completely read by the host.

Notes:

• SRC_OVF is not set if at least one of the OUT_X/Y/Z registers was read before the new data set

arrives.

• Whenever the INT_STATUS register is read, SRC_OVF is cleared.

• Whenever BUF_CONFIG1[BUF_MODE[1:0]] > 00b (buffer enabled), SRC_OVF is held at logic '0'.

Table 22. INT_STATUS register (address 00h) bit description

FXLS8974CF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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