FXLS8974CF datasheet(41/96 Pages) NXP

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NXP Semiconductors

FXLS8974CF

3-Axis Low-g Accelerometer

15.9 WHO_AM_I register (address 13h)

This register contains the NXP unique sensor product identifier and is factory

programmed to 86h for FXLS8974CF.

Bit

Name

WHO_AM_I[7:0]

Reset

Access

Table 44. WHO_AM_I register (address 13h) bit allocation

15.10 SYS_MODE register (address 14h)

The

SYS_MODE register indicates the current device operating mode. Applications

using the Auto-WAKE/SLEEP mechanism should use this register to synchronize their

application with FXLS8974CF operating mode transitions. This register also indicates the

status of the buffer gate error flag and the buffer gate count.

Bit

Name

BUF_

GATE_

ERR

BUF_GATE_CNT[4:0]

SYS_MODE[1:0]

Reset (BT_MODE = GND)

—

Reset (BT_MODE = VDD)

—

Access

Table 45. SYS_MODE register (address 14h) bit allocation

Field

Description

BUF_GATE_ERR

Buffer gate error flag:

0: A buffer gate error has not been detected

1: A buffer gate error was detected.

BUF CONFIG1[BUF _GATE] = 1 and the output buffer is not emptied before the arrival of the

next XYZ acceleration sample, the BUF _GATE_ERR flag is asserted. The BUF GATE_ERR flag

remains asserted as long as the output buffer remains un-emptied.

The BUF GATE_ERR flag may be cleared in one of the following ways:

1. Reading out the entire contents of the output buffer such that

BUF _STATUS[BUF_CNT[5:0]]

= 0.

2. Flushing (clearing) the output buffer contents by setting

BUF_CONFIG2[BUF _FLUSH] = 1.

3. Disabling the output buffer by setting

BUF _CONFIG1[BUF MODE[1:0]] = 00b, which clears

BUF_CNT.

4. Transitioning FXLS8974CF from Standby to Active mode.

Table 46. SYS_MODE register (address 14h) bit description

FXLS8974CF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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