FXLS8974CF datasheet(16/96 Pages) NXP

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NXP Semiconductors

FXLS8974CF

3-Axis Low-g Accelerometer

primary toggles the clock (SCLK). The SCLK polarity is defined as having an idle value

that is low, and an active phase that is high (CPOL = 0). Serial input and output data is

captured on the rising edge of the clock and propagated on the falling edge (CPHA =

0). Single-byte read and single-byte write operations are completed in 24 SCLK cycles;

multiple-byte reads and writes are completed in additional multiples of 8 SCLK cycles

per read or written byte. The first SCLK cycle latches the R/W (Read/Write) bit to select

whether the desired operation is a read (R/W = 1) or a write (R/W = 0). The following

seven SCLK cycles are used to latch the register read or write address.

Note: 4-wire SPI interface mode is the default out of POR or after a soft reset. In order

to select 3-wire SPI interface mode, set the

SENS_CONFIG1[SPI_M] = 1.

13.2 SPI write operations with 3- or 4-wire mode

A write operation is initiated by transmitting a 0 for the R/W bit. Then, the 7-bit register

write address, A[6:0], is transmitted in MSB first order. Following this first byte, a second

byte of 0s or 1s (don't care condition) transfers, followed by the actual data to write in the

third group of 8 SCLK cycles (clock pulses 17 through 24) in MSB first order. Figure 6

shows the bus protocol for a single-byte register write operation in either 3- or 4-wire SPI

mode.

aaa-040838

A6 A5 A4 A3 A2

R/W

A1 A0

High-Impedance

SPI_MISO

SPI_MOSI

SCLK

SPI_CS_B

D7 D6 D5 D4 D3 D2 D1 D0 X

Figure 6. SPI single-byte write protocol diagram (3- or 4-wire mode), R/W = 0

Multiple-byte write operations are performed similarly to the single-byte write sequence,

but with additional data bytes transferred over additional 8 SCLK cycle periods.

FXLS8974CF auto-increments the register write address so that every eighth clock edge

latches the address for the next register write address. When the desired number of

bytes has been written, a rising edge on the SPI_CS_B pin terminates the transaction.

Figure 7 shows the bus protocol for multiple-byte register write operations in either 3- or

4-wire SPI mode.

aaa-040839

High-Impedance

SPI_MISO

SPI_MOSI

SCLK

SPI_CS_B

10 11

12 13

15 16

19 20

21 22

23 24 25 26

27 28 29 30

A5 A4 A3 A2

R/W

A1 A0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 7. SPI multiple-byte write protocol diagram (3- or 4-wire mode), R/W = 0

13.3 SPI read operations with 4-wire mode

A register read operation is initiated by transmitting a 1 for the R/W bit. Then, the 7-

bit register read address, A[6:0] is encoded in the first byte. Following this first byte, a

FXLS8974CF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

16 / 96

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