FXLS8974CF datasheet(15/96 Pages) NXP

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NXP Semiconductors

FXLS8974CF

3-Axis Low-g Accelerometer

bytes of data can be written to sequential registers after each acknowledgment (ACK) is

received.

12.1.2.5 I2C data sequence diagrams

aaa-040837

Device Address[6:0]

Legend

Primary

Secondary

Primary

Secondary

Primary

Secondary

Primary

Secondary

Primary

ST: Start Condition

SP: Stop Condition

ACK: Acknowledge

NACK: No Acknowledge W: Write = 0

SR: Repeated Start Condition

Secondary

SR Device Address[6:0] R

NACK

ACK

DATA[7:0]

ACK

DATA[7:0]

continued

Device Address[6:0]

Device Address[6:0] R

ACK

NACK SP

Data[7:0]

ACK

Device Address[6:0]

Data[7:0]

ACK

Device Address[6:0]

Data[7:0]

ACK

Figure 5. I2C Data Sequence Diagrams

13 SPI interface

The SPI interface is a classic primary/secondary serial port. FXLS8974CF is always

considered to be the secondary device and therefore never initiates communication with

the host processor.

The SPI interface of FXLS8974CF is compatible with interface mode 00, corresponding

to CPOL = 0 and CPHA = 0.

For CPOL = 0, the idle value of the clock is zero, and the active value of the clock is 1.

For CPHA = 0, data is captured on the rising edge (low to high transition) of the clock,

and data is propagated on the falling edge (high to low transition) of the clock.

13.1 General SPI operation

The SPI_CS_B pin is driven low at the start of a transaction, held low during the transfer,

and then driven high again after the transaction is completed. During a transaction, the

FXLS8974CF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

15 / 96

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