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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCP3461RT-E/ST датащи(PDF) 10 Page - Microchip Technology |
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MCP3461RT-E/ST датащи(HTML) 10 Page - Microchip Technology |
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10 / 118 page  MCP3461/2/4R DS20006404C-page 10 2020-2021 Microchip Technology Inc. ADC Timing Parameters Sampling Frequency DMCLK See Table 5-6 MHz See Figure 4-1 Output Data Rate DRCLK See Table 5-6 ksps See Figure 4-1 Data Conversion Time TCONV See Table 5-6 ms See Figure 4-1 ADC Start-up Delay TADC_SETUP — 256 — DMCLK periods ADC_MODE[1:0] bits change from ‘0x’ to ‘1x’ —0 — DMCLK periods ADC_MODE[1:0] bits change from ‘10’ to ‘11’ Conversion Start Pulse Low Time TSTP —1 — DMCLK periods Scan Mode Time Delays TDLY_SCAN 0 — 512 DMCLK periods Time delay between sampling channels TTIMER_SCAN 0 — 16777215 DMCLK periods Time interval between Scan cycles Data Ready Pulse Low Time TDRL — — OSR-16 DMCLK periods See Figure 5-16 Data Ready Pulse High Time TDRH 16 — — DMCLK periods See Figure 5-16 Data Transfer Time to DR (Data Ready) tDODR — — 50 ns Modulator Output Valid from AMCLK High tDOMDAT — — 100 ns 2.7V ≤ DVDD ≤ 3.6V 200 1.8V ≤ DVDD ≤ 2.7V External Master Clock Input (CLK_SEL[1] = 0) Master Clock Input Frequency Range fMCLK_EXT 1— 20 MHz DVDD ≥ 2.7V 1— 10 MHz DVDD <2.7V Master Clock Input Duty Cycle fMCLK_DUTY 45 — 55 % Internal Clock Oscillator Internal Master Clock Frequency fMCLK_INT 3.3 — 6.6 MHz CLK_SEL[1] = 1 Internal Oscillator Start-up Time tOSC_STARTUP — 10 — µs CLK_SEL[1] changes from ‘0’ to ‘1’, time to stabilize the clock frequency to ±1 kHz of the final value (Note 10) Internal Oscillator Current Consumption IDDOSC — 30 — µA Should be added to DIDD when CLK_SEL[1:0] = 1x Internal Temperature Sensor Temperature Measurement Accuracy TAcc — ±5 — °C See Section 5.1.2 “Internal Temperature Sensor” ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD +0.1V, MCLK = 4.9152 MHz, VREF =AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions, TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameters Sym. Min. Typ. Max. Units Conditions Note 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: REFIN- must be connected to ground for single-ended measurements. 4: Full-Scale Range (FSR) = 2 x VREF/Gain. 5: This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical Performance Curves”. 7: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 8: DIDD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on REFIN+/OUT pin. |
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