MCP3461RT-ESLASHST datasheet(31/118 Pages) MICROCHIP

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DS20006404C-page 31

MCP3461/2/4R

3.3.3

SERIAL DATA OUTPUT PIN (SDO)

This pin is used for the SPI Data Output (SDO). The

SDO data are clocked out on the falling edge of SCK.

This pin stays high-impedance under the following

conditions:

• When CS pin is logic high.

• During the entire SPI Write or Fast command

communication period after the SPI COMMAND

byte has been transmitted.

• After the two device address bits in the command

are transmitted if the device address in the com-

mand does not match the internal chip device

address.

3.3.4

SERIAL DATA INPUT PIN (SDI)

This is the SPI Data Input (SDI) pin and it uses a

Schmitt Trigger structure. When CS is logic low, this

pin is used to send a COMMAND byte just after the CS

falling edge, which can be followed by data words of

various lengths. Data are clocked into the device on

the rising edge of SCK. Toggling SDI while reading a

3.4

IRQ/MDAT

This is the digital output pin. This pin can be configured for

Interrupt (IRQ) or Modulator Data (MDAT) output using

the IRQ_MODE[1] bit setting. When IRQ_MODE[1] = 0

(default), this pin can output all four possible interrupts

(see Section 6.8 “Interrupts Description”). The

Inactive state of the pin is selectable through the

IRQ_MODE[0] bit setting (high-Z or logic high).

When IRQ_MODE[1] = 1, this pin outputs the modulator

output synchronously with AMCLK (that can be

selected as an output on the MCLK pin). In this mode,

the POR and CRC interrupts can still be generated as

they are high-level interrupts, and will lock the

IRQ/MDAT pin to logic low until they are cleared.

When the IRQ pin is in High-Z mode, an external

pull-up resistor must be connected between DVDD and

the IRQ pin. The device needs to be able to detect a

Logic High state when no interrupt occurs in order to

function properly (the pad has an input Schmitt Trigger

to detect the state of the IRQ pin just like the user sees

it). The pull-up value can be equal to 100-200 k

 for a

weak pull-up using the typical clock frequency. The

pull-up resistor value must be selected in relation with

the load capacitance of the IRQ output, the MCLK

frequency and the DVDD supply voltage, so that all

interrupts can be correctly detected by the SPI host

device.

3.5

MCLK

This pin is either the MCLK digital input pin for the ADC

or the AMCLK digital output pin, depending on the

CLK_SEL[1:0] bits setting in the CONFIG0 register.

The typical clock frequency specified is 4.9152 MHz.

To optimize the ADC for accuracy and ensure proper

operation, AMCLK should be limited to a certain range

depending on the Boost and Gain settings. The higher

Gain settings require higher BOOST settings to main-

tain high bandwidth, as the input sampling capacitors

have

larger

value.

Figure 2-35,

Figure 2-36,

Figure 2-37, Figure 2-38 and Figure 2-43 represent the

typical accuracy (SINAD) expected with the different

combinations of Boost and Gain settings, and can be

used to determine an optimal set for the application

depending on the sampling speed (AMCLK) chosen.

MCLK can take larger values as long as the prescaler

settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in

the range shown in Section 2.0 “Typical Performance

Curves”.

3.6

Digital Ground (DGND)

DGND is the ground connection to internal digital

circuitry. To ensure accuracy and noise cancellation,

DGND must be connected to the same ground as

AGND, preferably with a star connection. If a digital

ground plane is available, it is recommended that this

pin be tied to this plane of the Printed Circuit Board

(PCB). This plane should also reference all other

digital circuitry in the system. DGND is not internally

connected to AGND and must be connected externally.

3.7

Digital Power Supply (DVDD)

DVDD is the power supply pin for the digital circuitry

within the device. The voltage on this pin must be

maintained in the range specified by the Electrical

Characteristics table. For optimal performance, it is

recommended to connect appropriate bypass capaci-

tors (typically a 10 µF ceramic in parallel with a 0.1 µF

ceramic). DVDD is monitored by the DVDD POR

monitoring circuit for the digital section.

3.8

Analog Power Supply (AVDD)

AVDD is the power supply pin for the analog circuitry

within the device. The voltage on this pin must be

maintained in the range specified by the Electrical

Characteristics table. For optimal performance, it is

recommended to connect appropriate bypass capaci-

tors (typically a 10 µF ceramic in parallel with a 0.1 µF

ceramic). AVDD is monitored by the AVDD POR

monitoring circuit for the analog section.

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