MCP3461RT-ESLASHST datasheet(41/118 Pages) MICROCHIP

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DS20006404C-page 41

MCP3461/2/4R

5.2

Input Impedance

The ADC inputs (VIN+/VIN-) are directly tied to the

analog multiplexer outputs and are not routed to exter-

nal pins. The multiplexer input stage contribution to the

input impedance is negligible.

The conversion accuracy can be affected by the input

signal source impedance when any external circuit is

connected to the input pins. The source impedance

adds to the internal impedance and directly affects the

time required to charge the internal sampling capacitor.

Therefore, a large input source impedance connected

to the input pins can increase the system performance

errors, such as offset, gain and Integral Nonlinearity

(INL). Ideally, the input source impedance should be

near zero. This can be achieved by using an opera-

tional amplifier with a closed-loop output impedance of

tens of ohms.

A proper anti-aliasing filter must be placed at the ADC

inputs. This will attenuate the frequency contents

around DMCLK and keep the desired accuracy over

the baseband (DRCLK) of the converter.

This anti-aliasing filter can be a simple first-order RC

network with low time constant, which will provide a

high rejection at the DMCLK frequency (see Figure 5-6

for more details). The RC network usually uses small R

and large C to avoid additional offset due to IR drop in

the signal path. This anti-aliasing filter will induce a

small systematic gain error on the AC input signals that

can be compensated in the digital section with the

Digital Gain Error Calibration (GAINCAL) register.

5.3

ADC Programmable Gain

The gain of the converter is programmable and

controlled by the GAIN[2:0] bits in the CONFIG2 register.

The ADC programmable gain is divided in two gain

stages: one in the analog domain, one in the digital

domain, as per Table 5-3.

After the multiplexer, the analog input signals are

routed to the Delta-Sigma ADC inputs and are

amplified by the analog gain stage (see Section 5.3.1

“Analog Gain” for more details). The digital gain stage

is placed inside the digital decimation filter (see

Section 5.3.2 “Digital Gain” for more details).

TABLE 5-3:

DELTA-SIGMA ADC GAIN SETTINGS

GAIN[2:0]

Total Gain

(V/V)

Analog Gain

(V/V)

Digital Gain

(V/V)

Total Gain

(dB)

VIN Range (V)

0.333

-9.5

±Min (AVDD, 3 * VREF)

±VREF

±VREF/2

±VREF/4

±VREF/8

±VREF/16

±VREF/32

±VREF/64

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