MCP3461RT-ESLASHST datasheet(57/118 Pages) MICROCHIP

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DS20006404C-page 57

MCP3461/2/4R

5.12.3

INTERNAL MASTER CLOCK

MODES (CLK_SEL[1:0] = 1x)

When CLK_SEL[1] = 1, the internal oscillator is selected

and the master clock is generated internally. The internal

oscillator has no Reset feature and continues to run

once selected. The master clock generation is indepen-

dent of the ADC as the clock can still be generated, even

if the ADC is in ADC Shutdown mode. The internal

oscillator is only disabled when CLK_SEL[1:0] = 0x. The

clock can be distributed to the dedicated output pin

depending on the CLK_SEL[0] bit. When the clock

output is selected (CLK_SEL[0] = 1), the AMCLK clock

derived from the MCLK (AMCLK = MCLK/PRESCALE)

is available on the output pin. The AMCLK output can

serve as the clock pin to synchronize the modulator out-

put or other MCP3461/2/4R devices that are configured

with CLK_SEL[1:0] = 00 or 01.

The AMCLK output is available on the MCLK clock

output pin as soon as the Write command

(CLK_SEL[1:0] = 11) is finished.

5.13

Digital System Offset and Gain

Calibrations

The

MCP3461/2/4R

devices

include

digital

calibration feature for offset and gain errors. The cali-

bration scheme for offset error consists of the addition

of a fixed offset value to the ADC output code

(ADCDATA at address: 0x0). The offset value added

(OFFSETCAL) is determined in the OFFSETCAL

error consists of the multiplication of a fixed gain value

to the ADCDATA code. The gain value (GAINCAL)

multiplied is determined in the GAINCAL register

(address: 0xA).

The digital offset and gain calibration schemes are

enabled or disabled via the EN_OFFCAL and

EN_GAINCAL control bits of the CONFIG3 register.

When both calibration control bits are enabled

(EN_OFFCAL = EN_GAINCAL = 1), the ADCDATA

bration schemes, as described in Equation 5-6. When a

calibration enable bit is off, its corresponding register

becomes a Don’t Care register and the corresponding

calibration is not performed.

EQUATION 5-6:

ADCDATA OUTPUT

AFTER DIGITAL GAIN

AND OFFSET ERROR

CALIBRATION

The calculations are performed internally with proper

management of overloading, so that the overload

detection is done on the output result only and not on

the intermediate results. A sufficient number of addi-

tional overload bits are maintained and propagated

internally to overcome all possible overload and/or

overload recovery situations.

For example, if ADCDATA (pre-calibration) + OFFSETCAL

is out of bounds, but (ADCDATA (pre-calibration) +

OFFSETCAL) x GAINCAL is still in the right range

(possible with 0 < GAINCAL < 1), the result is not

saturated.

5.13.1

DIGITAL OFFSET ERROR

CALIBRATION

The

Offset

Calibration

(OFFSETCAL,

address: 0x9) is a signed MSb first, two’s complement

coding, 24-bit register that holds the digital offset

calibration value, OFFSETCAL. The OFFSETCAL

equivalent input voltage value is calculated with

Equation 5-7.

EQUATION 5-7:

OFFSETCAL

CALIBRATION VALUE

(EQUIVALENT INPUT

VOLTAGE)

For the MCP3461/2/4R devices, the offset calibration

is done by adding the OFFSETCAL[23:8] calibration

value to the ADCDATA output code, bit by bit. The last

byte of the OFFSETCAL register (OFFSETCAL[7:0])

is ignored and internally reset to 0x00 during the cali-

bration; therefore, the addition just takes into account

the OFFSETCAL[23:8] bits and is done bit-by-bit with

the ADC output code.

The offset calibration value range in equivalent voltage

is [-VREF/GAIN; (+VREF – 1 LSb)/GAIN], which can

cancel any possible offset in the ADC but also in the

system. The offset calibration is realized with a simple

24-bit signed adder and is instantaneous (no pipeline

delay). Enabling the offset calibration will affect the

next conversion result; the conversion result already

held in the ADCDATA register (0x0) is not modified

when the EN_OFFCAL is set to ‘1’, but the next one

will take the offset calibration into account. Changing

the OFFSETCAL register to a new value will not affect

the current ADCDATA value, but the next one (after a

data ready interrupt) will take the new OFFSETCAL

value into account. Figure 5-12 presents the different

cases and their impact on the ADCDATA register and

the IRQ output.

ADCDATA (post-calibration) =

[ADCDATA (pre-calibration) + OFFSETCAL] x GAINCAL

OFFSETCAL (V) = VREF x (OFFSETCAL[23:8]

signed decimal code)/(32768 x GAIN)

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