FUSB308B datasheet(37/53 Pages) ONSEMI

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FUSB308B

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Table 29. PWRSTAT

Address: 1Eh

Reset Value: 08h

Type: Read

Bit #

Name

R/W/C

Size (Bits)

Power Status Description (Note 30)

DEBUG_ACC

Debug Accessory Attached

0b: No Debug Accessory Connected

1b: Debug Accessory Connected

Reflects the state of the DEBUG_ACC Output if present

TCPC_INIT

FUSB308B Initialization Status

0b: The FUSB308B has completed initialization and all registers

are valid

1b: The FUSB308B is still performing internal initialization.

Registers 00−0Fh are valid

SOURCE_HV

Sourcing High Voltage. See Transition Flow Charts for details.

0b: vsafe5V

1b: High Voltage

SOURCE_VBUS

Sourcing VBUS. Output SRC asserted.

0b: Sourcing VBUS is disabled

1b: Sourcing VBUS is enabled

VBUS_VAL_EN

VBUS_VAL (below) Detection Circuit Status

0b: VBUS_VAL Detection is Disabled

1b: VBUS_VAL Detection is Enabled

VBUS_VAL

VBUS Present

0b: VBUS disconnected (below 3.5 V)

1b: VBUS connected (Above 4.0 V)

VCONN_VAL

VCONN Present

0b: VCONN is not present or PWRCTRL.EN_VCONN is disabled

1b: This bit is asserted when VCONN is present on CC1 or CC2

Threshold is fixed at 2.4 V

SNKVBUS

Sink VBUS. Output SNK asserted.

0b: Sink is disconnected or not supported

30.An event change on this register cause an ALERTL.I_PWRSTAT Interrupt.

Table 30. FAULTSTAT

Address: 1Fh

Reset Value: 0x80

Type: Read/Write 1 to Clear

Bit #

Name

R/W/C

Size (Bits)

Fault Status Interrupt Description (Note 32)

ALL_REGS_RESET

(Note 31)

R/WC

0b: No reset occurred

1b: POR or unexpected power reset occurred

This bit is asserted when the TCPC resets all registers to their de-

fault value. This happens at initial power up or if an unexpected

power reset occurs

Reserved

Reserved: 0b

AUTO_DISCH_FAIL

R/WC

0b: No Discharge Failure

1b: VBUS Discharge Failed

Asserts when PWRCTRL.AUTO_DISCH is set and FUSB308B fails

to discharge VBUS to vSafe5V (max.) within tSafe5V or

vSafe0V(max.) within tSafe0V from disconnection is detected.

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