FUSB308B datasheet(42/53 Pages) ONSEMI

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FUSB308B

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Table 37. MSGHEADR

Address: 2Eh

Reset Value: FUSB308B: 0x0B

Type: Read/Write

Bit #

Name

R/W/C

Size (Bits)

Message Header Info Description

7:5

Reserved

Reserved: 000b

CBL_PLUG

R/W

Cable Plug

0b: Message originated from Source, Sink, or DRP

1b: Message originated from a Cable Plug

DATA_ROLE

R/W

Data Role

0b: SINK

1b: SOURCE

2:1

USBPD_REV

R/W

USB−PD Specification Revision

00b: Revision 1.0

01b: Revision 2.0

10b – 11b: Reserved

POWER_ROLE

R/W

Power Role

0b: Sink

1b: Source

Table 38. RXDETECT

RXDETECT enables the types of messages and/or signaling to be detected. SOP* enabling also turns on auto−GoodCRC response.

This register is reset when: A Hard Reset is received or sent; after the GoodCRC transmission due to RxOneMore; on a disconnect

detection; SW_RST or POR.

Address: 2Fh

Reset Value: 0x00

Type: Read/Write

Bit #

Name

R/W/C

Size (Bits)

Receive Detect Description (Note 34)

Reserved

Reserved: 0b

EN_CABLE_RST

0b: Do not detect Cable Reset signaling

EN_HRD_RST

R/W

0b: Do not detect Hard Reset signaling (default)

1b: Detect Hard Reset signaling

EN_SOP2_DBG

R/W

0b: Do not detect SOP_DBG” message (default)

1b: Detect SOP_DBG” message

EN_SOP1_DBG

R/W

0b: Do not detect SOP_DBG’ message (default)

1b: Detect SOP_DBG’ message

EN_SOP2

R/W

0b: Do not detect SOP” message (default)

1b: Detect SOP” message

EN_SOP1

R/W

0b: Do not detect SOP’ message (default)

1b: Detect SOP’ message

EN_SOP

R/W

0b: Do not detect SOP message (default)

1b: Detect SOP message

34.Writing all 0s to this register disables PD.

Table 39. RXBYTECNT

Address: 30h

Reset Value: 0x00

Type: Read

Bit #

Name

R/W/C

Size (Bits)

Received Byte Count Description

7:0

RXBYTECNT

Number of Bytes Received. This is the number of bytes in RX-

DATA plus 3 (RXSTAT and RXHEADL, H)

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