FUSB308B datasheet(10/53 Pages) ONSEMI

10 / 53 page

FUSB308B

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Hard Reset/ Cable Reset State Machine

The TCPM will write the TRANSMIT register to initiate

the Hard Reset/Cable Reset state machine, see Figure 8. If

a the FUSB308B is in the middle of a transmission when

instructed to send a Hard or Cable reset, it will set the

ALERTL.I_TXDISC bit and send the hard reset signaling as

soon as possible. The FUSB308B implements the

HardResetCompleteTimer. A Hard Reset or Cable Reset

will be attempted until the HardResetCompleteTimer times

out. After a successful transmission or timeout, the

FUSB308B will indicate that a Hard Reset or Cable Reset

has been sent by asserting both ALERTL.I_TXSUCC and

ALERTL.I_TXFAIL registers simultaneously. The bits in

RXDETECT and RXBYTECNT will be reset to disable PD

message passing after a Hard Reset is received or

transmitted.

Figure 8. Hard Reset and Cable Reset State Machine

TRANSMIT[2:0]=101b or 110b

written

Hard Reset or Cable Reset sent

tHardResetComplete

expires

PRL_HR_Wait_for_Hard_Reset_

Request

PRL_HR_Failure

Actions on entry:

Instruct PHY to stop attempting to

send Hard Reset or Cable Reset.

PRL_HR_Success

Actions on entry:

Stop tHardResetComplete timer

PRL_HR_Construct_Message

Actions on entry:

Start tHardResetComplete timer

Request PHY to send Hard Reset or

Cable Reset

Actions on entry:

PRL_HR_Report

Actions on entry:

Assert ALERT.I_TX_SUCC and

ALERT.I_TX_FAIL

Automatic GoodCRC Response

Power

Delivery

packets

require

GoodCRC

acknowledge packet to be sent for each received packet

where the calculated CRC is the correct value. This

calculation is done by the FUSB308B.

The FUSB308B will automatically send the GoodCRC

control packet in response to alleviate the local processor

from responding quickly to the received packet. Once the

GoodCRC packet is sent the FUSB308B will trigger the

ALERTL.I_RXSTAT interrupt.

The following sequence of events occur internally within

the FUSB308B without processor intervention when it is

determined that the receive message has the correct CRC. If

the host processor attempts a packet transmission during an

Automatic GoodCRC response, the FUSB308B will set the

ALERTL.I_TXDISC bit interrupting the processor. The

processor should only transmit a new packet once

ALERTL.I_TXSUCC or ALERTL.I_TX_FAIL has been

received.

It is assumed that the processor will set the

PWRCTRL.ORIENT to specify which channel USB−PD

traffic will be transmitted or received.

BIST Mode

Bist Transmit

The FUSB308B will transmit Bist Carrier Mode 2

signaling when directed by the TCPM via TRANSMIT

tBISTContMode timer expires.

Bist Receive

When the FUSB308B is in Bist receive mode via

TCPC_CTRL register, it will acknowledge these packets

with a GoodCRC and automatically flush the buffer to allow

for thousands of packets to be received without filling the

receive buffer. Bist Receive mode will exit on a cable

disconnect or a Hard Reset received.

VBUS Source Control

The FUSB308B has two source path controls (SRC and

SRC_HV). The secondary Source path control will be used

to provide higher voltages on VBUS after a PD contract has

been established. The primary source path is used for

sourcing vsafe5V only.

The TCPM will initiate the transition from SRC to

SRC_HV by writing 1000_1000b to the COMMAND

disable the SRC I/O.

When transitioning from a high voltage source to vsafe5V,

the TCPM will write 0111_0111b to the COMMAND

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