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FUSB308B датащи(PDF) 31 Page - ON Semiconductor

номер детали FUSB308B
подробное описание детали  USB Type-C Port Controller with USB-PD
PDF  53 Pages
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производитель  ONSEMI [ON Semiconductor]
домашняя страница  http://www.onsemi.com
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FUSB308B датащи(HTML) 31 Page - ON Semiconductor

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Table 18. ALERTH
Address: 11h
Reset Value: 0x00
Type: Read, Write 1 to Clear
Bit #
Name
R/W/C
Size (Bits)
ALERT2 Description
7
I_VS_ALERT
RWC
1
Vendor Defined Alert
0b: Cleeared
1b: A Vendor Defined Alert occurred. Please read
ALERT_VD register
6:4
Reserved
R
3
Reserved: 000b
3
I_VBUS_SNK_DISC
RWC
1
VBUS Sink Disconnect Detected
0b: Cleared
1b: A VBUS Sink Disconnect Threshold crossing from High to Low
has been detected
2
I_RX_FULL
RWC
1
Rx Buffer Overflow
0b: Internal RX Buffer is functioning properly
1b: Internal RX Buffer has overflowed
Note: This interrupt indicates overflow of the internal buffer, not the
RXDATA space. To clear overflow condition, write to ALERTL.I_RX-
STAT
Writing a 1 to this register acknowledges the overflow.
The actual overflow is cleared by writing to ALERTL. I_RXSTAT
1
I_FAULT
(Note 17)
R/WC
1
Fault Alarm
0b: Cleared
1b: A Fault alarm has occurred. Read FAULTSTAT register
0
I_VBUS_ALRM_LO
R/WC
1
Voltage Alarm Lo
0b: Cleared
1b: A low−voltage alarm has occurred
17.ALERTH.I_FAULT is asserted if the bit−wise AND of FAULTSTAT and FAULTSTAMSK results in any bits that have the value 1.
Table 19. ALERTMSKL
Address: 12h
Reset Value: 0xFF (Resets on POR, SW_RST and Hard Reset)
Type: Read/Write
Bit #
Name
R/W/C
Size (Bits)
Alert Mask 1 Description
7
M_VBUS_ALRM_HI
R/W
1
0b: Interrupt masked
1b: Interrupt unmasked
6
M_TXSUCC
R/W
1
0b: Interrupt masked
1b: Interrupt unmasked
5
M_TX_DISC
R/W
1
0b: Interrupt masked
1b: Interrupt unmasked
4
M_TXFAIL
R/W
1
0b: Interrupt masked
1b: Interrupt unmasked
3
M_RXHRDRST
R/W
1
0b: Interrupt masked
1b: Interrupt unmasked
Note: Generally this interrupt should not be masked.
2
M_RXSTAT
R/W
1
0b: Interrupt masked
1b: Interrupt unmasked
1
M_PORT_PWR
R/W
1
0b: Interrupt masked
1b: Interrupt unmasked
0
M_CCSTAT
R/W
1
0b: Interrupt masked
1b: Interrupt unmasked



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