USB333X datasheet(12/85 Pages) MICROCHIP

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USB333x

DS00001880A-page 12

 2009 - 2015 Microchip Technology Inc.

STP

Input,

CMOS

High

The Link asserts STP for one clock cycle to stop the

data stream currently on the bus. If the Link is sending

data to the PHY, STP indicates the last byte of data

was on the bus in the previous cycle.

VDD18

Power

N/A

1.8V Regulator Output. A 1.0uF (<1 ohm ESR) bypass

capacitor to ground is required for regulator stability.

The bypass capacitor should be placed as close as

possible to the USB333x.

RESETB

Input,

CMOS,

Low

When low, the part is suspended and the 3.3V and

1.8V regulators are disabled. When high, the

USB333x will operate as a normal ULPI device, as

described in Section 5.5.1. The state of this pin may

be changed asynchronously to the clock signals.

When asserted for a minimum of 1 microsecond and

then de-asserted, the ULPI registers are reset to their

default state and all internal state machines are reset.

REFCLK

Input,

CMOS

N/A

ULPI Clock Out Mode:

Frequency set by REF[1:0] pins.

ULPI Clock In Mode:

60MHz ULPI clock input.

RBIAS

Analog,

CMOS

N/A

Bias Resistor pin. This pin requires an 8.06kΩ (±1%)

resistor to ground, placed as close as possible to the

USB333x. Nominal voltage during ULPI operation is

0.8V.

GND

Ground

N/A

Ground.

TABLE 2-3:

USB3333 PIN DESCRIPTION

Ball

Name

Direction/

Type

Active

Level

Description

Input,

Analog

N/A

For device applications the ID pin is connected to

VDD33

. For Host applications ID is grounded. For

OTG applications the ID pin is connected to the USB

connector.

VBUS

I/O,

Analog

N/A

This pin is used for the VBUS comparator inputs and

for VBUS pulsing during session request protocol. An

external resistor, RVBUS, is required between this pin

and the USB connector.

VBAT

Power

N/A

Regulator input. The regulator supply can be from

5.5V to 3.0V.

VDD33

Power

N/A

3.3V Regulator Output. A 1.0uF (<1 ohm ESR) bypass

capacitor to ground is required for regulator stability.

The bypass capacitor should be placed as close as

possible to the USB333x.

I/O,

Analog

N/A

D- pin of the USB cable.

I/O,

Analog

N/A

D+ pin of the USB cable.

REF[0]

I/O,

Digital 3.3V

N/A

Used to select REFCLK frequency. Connect to ground

or VDD33. Refer to Table 5-2 for frequency selection

options.

VDDIO

Power

N/A

ULPI interface supply voltage. When RESETB is low

and VDDIO is powered on, ULPI pins will tri-state.

DATA[7]

I/O,

CMOS

N/A

ULPI bi-directional data bus. DATA[7] is the MSB.

DATA[6]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

TABLE 2-2:

USB3330 PIN DESCRIPTION (CONTINUED)

Ball

Name

Direction/

Type

Active

Level

Description

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